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fc?pbga?783 29 mm 29 mm freescale semiconductor data sheet: technical data ? 2008?2011 freescale semiconductor, inc. ? high-performance, 32-bit e500 core, scaling up to 1.33 ghz, that implements the power architecture? technology ? 2799 mips at 1.33 ghz (estimated dhrystone 2.1) ? 36-bit physical addressing ? double-precision embedded floating point apu using 64-bit operands ? embedded vector and s calar single-precision floating-point apus using 32- or 64-bit operands ? memory management unit (mmu) ? integrated l1/l2 cache ? l1 cache?32-kbyte data and 32-kbyte instruction ? l2 cache?512-kbyte (8-way set associative) ? two ddr2/ddr3 sdram memory controllers with full ecc support ? one 64-bit or two 32-bit data bus configuration ? up to 400 mhz clock (800 mhz data rate) ? supporting up to 16 gbytes of main memory ? using ecc, detects and correct s all single-bit errors and detects all double-bit errors an d all errors within a nibble ? invoke a level of system power management by asserting mcke sdram signal on-the-fly to put the memory into a low-power sleep mode ? both hardware and software options to support battery-backed main memory ? initialization bypass feature that allow system designers to prevent re-initialization of main memory during system power on following abnormal shutdown ? integrated security engine (sec) optimized to process all the algorithms associated with ipsec, ike, ssl/tls, iscsi, srtp, ieee std 802.11i?, ieee std 802.16? (wimax), ieee 802.1ae? (macsec), 3gpp, a5/3 for gsm and edge, and gea3 for gprs. ? xor engine for parity checking in raid storage applications ? four crypto-channels, each supporting multi-command descriptor chains ? cryptographic execution units for pkeu, deu, aesu, afeu, mdeu, keu, crcu, rng and seu- snow ? quicc engine technology ? four 32-bit risc cores ? supports ethernet, atm, pos, and t1/e1 along with associated interworking ? four gigabit ethernet interfaces (up to two with sgmii) ? up to eight 10/100-mbps ethernet interfaces ? up to 16 t1/e1 tdm links (512 64 channels) ? multi-phy utopia/pos-phy l2 interface (16-bit) ? ieee std 1588? v2 support ? spi and ethernet phy management interface ? one full-/low-speed usb interface supporting usb 2.0 ? general-purpose i/o signals ? high-speed interfaces (m ultiplexed) supporting: ? two 1 serial rapidio interfaces (with message unit) or one 4x interface ? 4/2/1 pci express interface ? two sgmii interfaces ? on-chip network switch fabric ? 133 mhz, 16-bit, 3.3 v i/o, enhanced local bus (elbc) with memory controller ? enhanced secured digital host controller (esdhc) used for sd/mmc card interface ? integrated four-channel dma controller ? dual i 2 c and dual universal asynchronous receiver/transmitter (duart) support ? programmable interrupt controller (pic) ? ieee std 1149.1? jtag test access port ? 1.0-v and 1.1-v core voltages with 3.3-v, 2.5-v, 1.8-v, 1.5-v and 1.0-v i/o ? 783-pin fc-pbga package, 29 mm 29 mm document number: mpc8569eec rev. 0, 06/2011 mpc8569e powerquicc iii integrated processor hardware specifications mpc8569e
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 2 table of contents 1 pin assignments and reset states . . . . . . . . . . . . . . . . . . . . .4 1.1 ball layout diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 pinout list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 2.1 overall dc electrical characteri stics . . . . . . . . . . . . . .36 2.2 power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .42 2.3 input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 2.4 ddr2 and ddr3 sdram controller . . . . . . . . . . . . . .45 2.5 duart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2.6 ethernet interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.7 ethernet management interface . . . . . . . . . . . . . . . . . .73 2.8 hdlc, bisync, transparent, and synchronous uart interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 2.9 high-speed serdes interfaces (hssi) . . . . . . . . . . . . .77 2.10 pci express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 2.11 serial rapidio (srio) . . . . . . . . . . . . . . . . . . . . . . . . .89 2.12 i 2 c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.13 gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 2.14 jtag controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 2.15 enhanced local bus controller . . . . . . . . . . . . . . . . .100 2.16 enhanced secure digital host controller (esdhc) . 107 2.17 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 2.18 programmable interrupt controller (pic). . . . . . . . . . 110 2.19 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 2.20 tdm/si . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 2.21 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 2.22 utopia/pos interface . . . . . . . . . . . . . . . . . . . . . . . 116 3 thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 3.1 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . 118 3.2 recommended thermal model . . . . . . . . . . . . . . . . . 118 3.3 thermal management information . . . . . . . . . . . . . . 119 4 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.1 package parameters for the mpc8569e . . . . . . . . . . 120 4.2 mechanical dimensions of the fc-pbga with full lid122 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.1 part numbers fully addressed by this document . . 123 5.2 part marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.3 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6 product documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . 125
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 3 note the mpc8569e is also available without a security engine in a configuration known as the mpc8569. all specifications other than those relating to security apply to the mpc8569 exactly as described in this document. the following figure shows the major functional units within the mpc8569e. figure 1. mpc8569e block diagram mpc8569e e500v2 core 32-kbyte d-cache 32-kbyte i-cache 512-kbyte l2 cache xor acceleration performance monitor duart 2i 2 c baud rate generators accelerators four 32-bit eriscs 4 gigabit ethernet utopia/ pos-phy l2 quicc engine block ucc4 ucc3 ucc2 ucc1 mcc1 128-kbyte muram communications interfaces ucc8 ucc7 ucc6 ucc5 eth mgmt time slot assigner spi1 & 2 usb mcc2 4-channel dma 256-kbyte iram serial dma interrupt controller up to 8 rmii up to 16 t1/e1 up to four-lane serdes on-chip network rio msg unit pci express serial rapidio serial rapidio sgmii sgmii enhanced secure digital controller one 64-bit or ddr2/ddr3 controller(s) two 32-bit local bus openpic coherency module e500 enhanced security engine
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ball layout diagrams freescale semiconductor 4 1 pin assignments and reset states 1.1 ball layout diagrams the following figure shows the top view of the mpc8569e 783-pin bga ball map diagram. figure 2. mpc8569e top view ballmap gv dd gnd d2_ mcke [3] d2_ modt [1] d2_ ma [1] d2_ ma [11] d2_ mcs [1] d2_ mdq [31] d2_ mdq [30] d2_ mdm [3] d2_ mdq [7] d2_ mdq [29] d2_ mdq [6] d2_ mdm [0] d2_ mdq [5] d2_ ma [15] d2_ ma [4] gv dd gnd d2_ mdq [27] gv dd gnd d2_ mdq [28] d2_ mdq [3] gv dd gnd d2_ mdq [0] d2_ modt [0] d2_ mcke [2] gv dd gnd d2_ mck [2] d2_ mck [2] d2_ mdq [26] d2_ mdq [25] d2_ mdqs [3] d2_ mdq [24] d2_ mdq [2] d2_ mdqs [0] d2_ mdqs [0] d2_ mdq [1] gv dd gnd d2_ ma [13] gv dd gnd d2_ ma [14] d2_ mecc [7] d2_ mecc [5] d2_ mdqs [3] gv dd gnd d2_ mdq [14] d2_ mdm [1] d2_ mdq [13] d2_ modt [3] d2_ mwe d2_ mcs [0] d2_ ma [0] d2_ ma [8] d2_ mba [2] d2_ mecc [6] d2_ mdm [8] d2_ mck [0] d2_ mck [0] d2_ mdq [15] gv dd gnd d2_ mdq [12] d2_ mapar_ out gv dd gnd d2_ mba [1] gv dd gnd d2_ mecc [3] gv dd gnd d2_ mecc [4] d2_ mdq [11] d2_ mdqs [1] d2_ mdq [9] d2_ mdq [8] d2_ mapar_ err d2_ mcs [3] d2_ ma [6] d2_ mras d2_ ma [9] d2_ ma [3] d2_ mcke [0] d2_ mecc [2] d2_ mdqs [8] d2_ mdqs [1] gnd gv dd d2_ modt [2] d2_ ma [5] gv dd gnd d2_ mcs [2] d2_ mecc [1] d2_ mdqs [8] gv dd gnd d2_ mdq [23] gv dd gnd d2_ mvref d2_ mdic [0] gv dd d2_ mcas d2_ mba [0] d2_ ma [10] d2_ ma [2] d2_ ma [7] d2_ ma [12] d2_ mck [1] d2_ mck [1] d2_ mdq [19] d2_ mdqs [2] d2_ mdq [17] avdd_ ce gnd gv dd gv dd gnd gv dd gnd d2_ mcke [1] gv dd gv dd gv dd gnd d2_ mdq [18] d2_ mdic [1] avdd_ core qe_pc [3] qe_pa [22] qe_pa [18] qe_pa [15] qe_pc [16] gnd gnd qe_pb [18] qe_pb [12] gnd v dd gnd gnd gnd lv dd2 qe_pa [23] qe_pa [20] qe_pa [16] lv dd2 qe_pc [17] qe_pb [19] lv dd2 qe_pb [13] v dd gnd v dd gv dd gnd v dd gnd v dd gnd gnd gnd gnd gnd gnd gnd v dd v dd v dd v dd gn d gn d gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd gnd gnd gnd v dd v dd v dd v dd v dd v dd v dd v dd gnd gnd gnd gnd gnd sense- v dd sense- v ss qe_pa [24] qe_pa [28] qe_pc [2] qe_pa [26] qe_pa [21] qe _p a [17] gnd qe_pc [24] qe_pb [20] gnd qe_pb [14] qe_pa [19] qe_pb [17] qe_pc [25] qe_pb [9] qe_pb [1] qe_pa [29] qe_pa [14] qe_pb [24] qe_pb [21] qe_pb [16] qe_pb [15] qe_pa [25] qe_pb [23] qe_pc [9] lv dd1 qe_pb [0] lv dd1 qe_pc [11] qe_pa [12] qe_pa [6] qe_pa [4] qe_pa [2] qe_pa [27] qe_pb [22] qe_pb [3] gnd qe_pa [31] gnd qe_pc [8] qe_pa [8] gnd lv dd1 qe_pa [0] qe_pe [22] qe_pe [14] qe_pe [16] qe_pe [11] qe_pe [10] qe_pe [17] qe_pb [25] qe_pb [4] qe_pb [5] qe_pb [6] qe_pa [30] qe_pc [20] qe_pa [9] qe_pa [7] qe _p a [3] qe_pa [1] qe_pb [7] qe_pb [8] qe_pb [10] qe_pb [2] qe_pc [29] qe_pa [13] qe_pa [11] qe_pa [10] qe_pa [5] qe_pc [5] qe_pc [0] qe_pc [1] qe_pc [6] ov dd qe_pc [7] qe_pc [26] qe_pc [27] ov dd qe_pb [11] ov dd qe_pc [22] qe_pc [23] qe_pc [19] gnd qe_pc [4] qe_pd [18] qe_pd [26] gnd qe_pd [21] gnd qe_pc [13] qe_pc [15] qe_pc [14] qe_pc [12] qe_pd [24] qe_pd [19] qe_pd [17] qe_pd [27] qe_pd [22] qe_pd [20] qe_pc [31] qe_pc [30] qe_pc [21] qe_pc [10] qe_pc [18] qe_pe [15] qe_pd [10] qe_pd [6] qe_pd [15] qe_pd [16] ov dd qe _p d [25] qe_pd [23] qe_pe [25] qe_pe [26] ldp [0] qe_pe [12] qe_pe [13] qe_pe [18] qe_pd [11] bv dd qe_pd [8] qe_pd [14] qe_pb [28] gnd qe_pf [10] qe_pf [11] qe_pe [24] qe_pf [4] lcs [3] qe_pe [21] qe_pe [19] qe_pe [20] qe_pd [5] gnd qe_pd [9] qe_pd [7] qe_pb [29] qe_pb [30] qe_pb [31] qe_pf [12] qe_pf [9] qe_pf [5] lcs4_ irq [8] qe_pe [23] ov dd qe_pe [5] qe_pd [4] qe_pd [12] qe_pd [13] qe_pe [31] qe_pf [2] qe_pf [16] qe_pf [15] ov dd qe_pf [7] qe_pf [3] la [18] qe_pd [28] gnd qe_pe [4] qe_pe [2] qe_pd [3] qe_pd [1] ov dd qe_pf [0] qe_pf [17] qe_pf [18] gnd qe_pf [6] qe_pc [28] lad [1] qe_pd [29] qe_pd [30] qe_pe [6] qe_pe [3] qe_pe [9] qe_pd [2] gnd qe_pf [1] qe_pf [21] qe_pe [28] qe_pe [30] qe_pf [8] qe_pb [26] lad [0] qe_pd [31] qe_pe [0] qe_pe [1] qe_pe [8] qe_pe [7] qe_pd [0] qe_pf [20] qe_pf [19] qe_pf [22] qe_pe [ 29] qe _pe [27] qe_pf [13] qe_pf [14] qe_pb [27] d1_ mcke [3] d1_ mdic [1] d1_ ma [1] d1_ ma [11] d1_ mdic [0] d1_ mdq [31] d1_ mdq [30] d1_ mdm [3] d1_ mdq [29] d1_ mdq [7] d1_ ma [13] d1_ mdq [6] d1_ mdm [0] d1_ mdq [5] d2_ mdq [4] gv dd gnd d1_ ma [4] gv dd gnd d1_ mdq [27] gv dd gnd d1_ mdq [28] d1_ mdq [3] gv dd gnd d1_ mdq [4] d1_ ma [15] d1_ modt [0] d1_ mcke [2] d1_ ma [6] d1_ mck [2] d1_ mck [2] d1_ mdq [26] d1_ mdq [25] d1_ mdqs [3] d1_ mdq [24] d1_ mdq [2] d1_ mdqs [0] d1_ mdq [1] d1_ mdq [0] gv dd gnd d1_ ma [14] d1_ mcs [0] gv dd gnd d1_ mecc [7] d1_ mecc [5] d1_ mdqs [3] gv dd gnd d1_ mdqs [0] gv dd gnd d1_ mapar_ out d1_ modt [3] d1_ mwe d1_ ma [0] d1_ ma [8] d1_ mba [2] d1_ mecc [6] d1_ mdm [8] d1_ mck [0] d1_ mck [0] d1_ mdq [15] d1_ mdq [14] d1_ mdm [1] d1_ mdq [13] d1_ mapar_ err gv dd gnd d1_ mba [1] gv dd gnd d1_ mecc [3] gv dd gnd d1_ mecc [4] d1_ mdq [11] gv dd gnd d1_ mdq [12] d2_ mdq [21] d1_ mcs [3] d1_ modt [2] d1_ mras d1_ ma [9] d1_ ma [3] d1_ mcke [0] d1_ mecc [2] d1_ mdqs [8] d1_ mecc [0] d1_ mdq [10] d1_ mdqs [1] d1_ mdq [9] d1_ mdq [8] d2_ mdq [20] gv dd gnd d1_ ma [5] d1_ ma [2] gv dd gnd d1_ mecc [1] d1_ mdqs [8] gv dd gnd d1_ mdqs [1] gv dd gnd d2_ mdq [16] d1_ modt [1] d1_ mcas d1_ ma [10] gv dd d1_ mcke [1] d1_ ma [7] d1_ ma [12] d1_ mck [1] d1_ mck [1] d1_ mdq [23] d1_ mdq [22] d1_ mdm [2] d1_ mdq [21] gnd d1_ mcs [1] d1_ mba [0] gv dd gnd d1_ mcs [2] gnd gv dd d1_ mdq [18] d1_ mdqs [2] d1_ mdq [19] gv dd gnd d1_ mdq [20] gnd gv dd gnd gv dd gnd d1_ mdqs [2] d1_ mdq [17] d1_ mdq [16] gnd irq_ out ude mcp asleep clk_ out rtc ov dd gnd avdd_ ddr irq4_ msrcid [3] tck tms ov dd gnd trig_in bvdd_ vsel [0] d1_ mvref avdd_ plat bvdd_ vsel [1] tdi trst tdo trig_out_ _ready__ quiesce sysclk lv d d _ vsel [1] gnd gnd irq [0] irq5_ msrcid [4] irq6_ dval xv dd xgnd irq [3] irq [2] score- v dd score- gnd gnd irq [1] rsvd sd_tx [0] sd_tx [0] score- gnd score- v dd sd_rx [0] sd_rx [0] rsvd rsvd gnd xv dd xgnd agnd_ srds avdd_ srds score- gnd score- v dd gnd xv dd xgnd sd_tx [1] sd_tx [1] score- gnd score- v dd sd_rx [1] sd_rx [1] gnd sd_pll_ tpd sd_imp_ cal_rx xgnd xv dd sd_ref_ clk sd_ref_ clk score- v dd score- gnd gnd xgnd xv dd sd_tx [2] sd_tx [2] score- v dd score- gnd sd_rx [2] sd_rx [2] ldp [1] lgpl [5] lgpl1_ lfale lgpl4_ lupwait_ lbpbse_ lfrb lgpl0_ lfcle lgpl3_ lfwp sd_tx_ clk xv dd xgnd sd_imp_ cal_tx sd_pll_ tpa score- gnd score- v dd gnd lcs [1] bv dd lcs [0] bv dd la [25] bv dd lcs7_ irq [11] xv dd xgnd sreset hreset_ req score- v dd score- gnd lcs [2] gnd lwe1_ lbs [1] gnd lwe0_ lbs0_ lfwe xv dd xgnd sd_tx [3] sd_tx [3] xgnd score- gnd sd_rx [3] sd_rx [3] la [16] la [17] la [19] la [21] la [23] lgpl2_ loe_ lfre lad [15] lcs6_ irq [10] hreset dma_ dack2_ sd_cmd dma_ ddone_ [0] dma_ dreq2_ sd_dat0 dma_ dack1_ msrcid1 lvd d_ vsel [0] lbctl la [20] la [22] la [24] la [26] lad [13] lad [12] la [27] lcs5_ irq [9] dma_ ddone1_ msrcid2 dma_ dreq1_ msrcid0 gnd ov dd ckstp_ in bv dd lclk [1] bv dd lclk [0] bv dd lad [7] bv dd lad [14] dma_ dack_ [0] ov dd dma_ ddone2_ sd_wp iic2_ scl_sd_ cd uart_ sin0_dma _dack3_ sd_dat2 ckstp_ out gnd lad [2] gnd lad [6] gnd lad [8] gnd lad [11] dma_ dreq_ [0] gnd iic2_ sda_sd_ clk iic1_ scl uart_ cts0_dma _ddone3_ sd_dat3 uart_ sout0_dma _dreq3_ sd_dat1 lsync_ out lsync_ in lad [3] lad [4] lad [5] lale lad [9] lad [10] gnd avdd_ lbiu gnd iic1_ sda lssd_ mode uart_ rts [0] ov dd d2_ mecc [0] d2_ mdq [10] d2_ mdq [22] d2_ mdm [2] sd_tx_ clk d2_ mdqs [2] 1 171615 14 13 12 11 10 98765432 18 19 20 21 22 23 24 25 26 27 28 w y aa ab ac ad ae af ag ah a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah 1 171615 14 13 12 11 10 98765432 18 a b c d e f g h j k l m n p r t u v 19 20 21 22 23 24 25 26 27 28 see detail a see detail b see detail d see detail c
ball layout diagrams mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 5 the following figure provides detailed view a of the mpc8569e 783-pin bga ball map diagram. figure 3. mpc8569e detail a ball map gv dd gnd d2_ mcke [3] d2_ modt [1] d2_ ma [1] d2_ ma [11] d2_ mcs [1] d2_ mdq [31] d2_ mdq [30] d2_ mdm [3] d2_ mdq [7] d2_ mdq [29] d2_ mdq [6] d2_ mdm [0] d2_ mdq [5] d2_ ma [15] d2_ ma [4] gv dd gnd d2_ mdq [27] gv dd gnd d2_ mdq [28] d2_ mdq [3] gv dd gnd d2_ mdq [0] d2_ modt [0] d2_ mcke [2] gv dd gnd d2_ mck [2] d2_ mck [2] d2_ mdq [26] d2_ mdq [25] d2_ mdqs [3] d2_ mdq [24] d2_ mdq [2] d2_ mdqs [0] d2_ mdqs [0] d2_ mdq [1] gv dd gnd d2_ ma [13] gv dd gnd d2_ ma [14] d2_ mecc [7] d2_ mecc [5] d2_ mdqs [3] gv dd gnd d2_ mdq [14] d2_ mdm [1] d2_ mdq [13] d2_ modt [3] d2_ mwe d2_ mcs [0] d2_ ma [0] d2_ ma [8] d2_ mba [2] d2_ mecc [6] d2_ mdm [8] d2_ mck [0] d2_ mck [0] d2_ mdq [15] gv dd gnd d2_ mdq [12] d2_ mapar_ out gv dd gnd d2_ mba [1] gv dd gnd d2_ mecc [3] gv dd gnd d2_ mecc [4] d2_ mdq [11] d2_ mdqs [1] d2_ mdq [9] d2_ mdq [8] d2_ mapar_ err d2_ mcs [3] d2_ ma [6] d2_ mras d2_ ma [9] d2_ ma [3] d2_ mcke [0] d2_ mecc [2] d2_ mdqs [8] d2_ mdqs [1] gnd gv dd d2_ modt [2] d2_ ma [5] gv dd gnd d2_ mcs [2] d2_ mecc [1] d2_ mdqs [8] gv dd gnd d2_ mdq [23] gv dd gnd d2_ mvref d2_ mdic [0] gv dd d2_ mcas d2_ mba [0] d2_ ma [10] d2_ ma [2] d2_ ma [7] d2_ ma [12] d2_ mck [1] d2_ mck [1] d2_ mdq [19] d2_ mdqs [2] d2_ mdq [17] avdd_ qe gnd gv dd gv dd gnd gv dd gnd d2_ mcke [1] gv dd gv dd gv dd gnd d2_ mdq [18] d2_ mdic [1] avdd_ core qe_pc [3] qe_pa [22] qe_pa [18] qe_pa [15] qe_pc [16] gnd gnd qe_pb [18] qe_pb [12] gnd v dd gnd gnd gnd lv dd2 qe_pa [23] qe_pa [20] qe_pa [16] lv dd2 qe_pc [17] qe_pb [19] lv dd2 qe_pb [13] v dd gnd v dd gnd v dd gnd v dd gnd sense- v dd qe_pa [24] qe_pa [28] qe_pc [2] qe_pa [26] qe _pa [21] qe_pa [17] gnd qe_pc [24] qe_pb [20] gnd qe_pb [14] qe_pa [19] qe_pb [17] qe_pc [25] qe_pb [9] qe_pb [1] qe_pa [29] qe_pa [14] qe_pb [24] qe_pb [21] qe_pb [16] qe_pb [15] d2_ mecc [0] d2_ mdq [10] d2_ mdq [22] d2_ mdm [2] d2_ mdqs [2] 1 14 13 12 11 10 98765432 a b c d e f g h j k l m n p detail a
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ball layout diagrams freescale semiconductor 6 the following figure provides detailed view b of the mpc8569e 783-pin bga ball map diagram. figure 4. mpc8569e detail b ball map gv dd gnd v dd gnd v dd gnd gnd gnd gnd gnd gnd v dd v dd v dd v dd v dd gnd v dd v dd sense- v ss d1_ mcke [3] d1_ mdic [1] d1_ ma [1] d1_ ma [11] d1_ mdic [0] d1_ mdq [31] d1_ mdq [30] d1_ mdm [3] d1_ mdq [29] d1_ mdq [7] d1_ ma [13] d1_ mdq [6] d1_ mdm [0] d1_ mdq [5] d2_ mdq [4] gv dd gnd d1_ ma [4] gv dd gnd d1_ mdq [27] gv dd gnd d1_ mdq [28] d1_ mdq [3] gv dd gnd d1_ mdq [4] d1_ ma [15] d1_ mo dt [0] d1_ mcke [2] d1_ ma [6] d1_ mck [2] d1_ mck [2] d1_ mdq [26] d1_ mdq [25] d1_ mdqs [3] d1_ mdq [24] d1_ mdq [2] d1_ mdqs [0] d1_ mdq [1] d1_ mdq [0] gv dd gnd d1_ ma [14] d1_ mcs [0] gv dd gnd d1_ mecc [7] d1_ mecc [5] d1_ mdqs [3] gv dd gnd d1_ mdqs [0] gv dd gnd d1_ mapar_ out d1_ modt [3] d1_ mwe d1_ ma [0] d1_ ma [8] d1_ mba [2] d1_ mecc [6] d1_ mdm [8] d1_ mck [0] d1_ mck [0] d1_ mdq [15] d1_ mdq [14] d1_ mdm [1] d1_ mdq [13] d1_ mapar_ err gv dd gnd d1_ mba [1] gv dd gnd d1_ mecc [3] gv dd gnd d1_ mecc [4] d1_ mdq [11] gv dd gnd d1_ mdq [12] d2_ mdq [21] d1_ mcs [3] d1_ modt [2] d1_ mras d1_ ma [9] d1_ ma [3] d1_ mcke [0] d1_ mecc [2] d1_ mdqs [8] d1_ mecc [0] d1_ mdq [10] d1_ mdqs [1] d1_ mdq [9] d1_ mdq [8] d2_ mdq [20] gv dd gnd d1_ ma [5] d1_ ma [2] gv dd gnd d1_ mecc [1] d1_ mdqs [8] gv dd gnd d1_ mdqs [1] gv dd gnd d2_ mdq [16] d1_ modt [1] d1_ mcas d1_ ma [10] gv dd d1_ mcke [1] d1_ ma [7] d1_ ma [12] d1_ mck [1] d1_ mck [1] d1_ mdq [23] d1_ mdq [22] d1_ mdm [2] d1_ mdq [21] gnd d1_ mcs [1] d1_ mba [0] gv dd gnd d1_ mcs [2] gnd gv dd d1_ mdq [18] d1_ mdqs [2] d1_ mdq [19] gv dd gnd d1_ mdq [20] gnd gv dd gnd gv dd gnd d1_ mdqs [2] d1_ mdq [17] d1_ mdq [16] gnd irq_ out ude mcp asleep clk_ out rtc ov dd gnd avdd_ ddr irq4_ msrcid [3] tck tms ov dd gnd trig_in bvdd_ vsel [0] d1_ mvref avdd_ plat bvdd_ vsel [1] tdi trst tdo sysclk lvdd_ vsel [1] gnd gnd 17 16 15 18 a b c d e f g h j k l m n p 19 20 21 22 23 24 25 26 27 28 detail b trig_out_ _ready__ quiesce
ball layout diagrams mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 7 the following figure provides detailed view c of the mpc8569e 783-pin bga ball map diagram. figure 5. mpc8569e detail c ball map gnd gnd v dd v dd v dd gnd gnd gnd gnd gnd v dd v dd v dd v dd v dd v dd gnd gnd qe_pa [25] qe_pb [23] qe_pc [9] lv dd1 qe_pb [0] lv dd1 qe_pc [11] qe_pa [12] qe_pa [6] qe_pa [4] qe_pa [2] qe_pa [27] qe_pb [22] qe_pb [3] gnd qe_pa [31] gnd qe_pc [8] qe_pa [8] gnd lv dd1 qe_pa [0] qe_pe [22] qe_pe [14] qe_pe [16] qe_pe [11] qe_pe [10] qe_pe [17] qe_pb [25] qe_pb [4] qe_pb [5] qe_pb [6] qe_pa [30] qe_pc [20] qe_pa [9] qe_pa [7] qe_pa [3] qe_pa [1] qe_pb [7] qe_ pb [8] qe_pb [10] qe_pb [2] qe_pc [29] qe_pa [13] qe_pa [11] qe_pa [10] qe_pa [5] qe_pc [5] qe_pc [0] qe_pc [1] qe_pc [6] ov dd qe_pc [7] qe_pc [26] qe_pc [27] ov dd qe_pb [11] ov dd qe_pc [22] qe_pc [23] qe_pc [19] gnd qe_pc [4] qe_pd [18] qe_pd [26] gnd qe_pd [21] gnd qe_pc [13] qe_pc [15] qe_pc [14] qe_pc [12] qe_pd [24] qe_pd [19] qe_pd [17] qe_pd [27] qe_pd [22] qe_pd [20] qe_pc [31] qe_pc [30] qe_pc [21] qe_pc [10] qe_pc [18] qe_pe [15] qe_pd [10] qe_pd [6] qe_pd [15] qe_pd [16] ov dd qe_pd [25] qe_pd [23] qe_p e [25] qe_pe [26] ldp [0] qe_pe [12] qe_pe [13] qe_pe [18] qe_pd [11] qe_pd [8] qe_pd [14] qe_pb [28] gnd qe_pf [10] qe_pf [11] qe_pe [24] qe_pf [4] lcs [3] qe_pe [21] qe_pe [19] qe_pe [20] qe_pd [5] gnd qe_pd [9] qe_pd [7] qe_pb [29] qe_pb [30] qe_pb [31] qe_pf [12] qe_pf [9] qe_pf [5] lcs4_ irq [8] qe_pe [23] ov dd qe_pe [5] qe_pd [4] qe_pd [12] qe_pd [13] qe_pe [31] qe_pf [2] qe_pf [16] qe_pf [15] ov dd qe_pf [7] qe_pf [3] la [18] qe_pd [28] gnd qe_pe [4] qe_pe [2] qe_pd [3] qe_pd [1] ov dd qe_pf [0] qe_pf [17] qe_pf [18] gnd qe_pf [6] qe_pc [28] lad [1] qe_pd [29] qe_pd [30] qe_pe [6] qe_pe [3] qe_pe [9] qe_pd [2] gnd qe_pf [1] qe_pf [21] qe_pe [28] qe_pe [30] qe_pf [8] qe_pb [26] lad [0] qe_pd [31] qe_pe [0] qe_pe [1] qe_pe [8] qe_pe [7] qe_pd [0] qe_pf [20] qe_pf [19] qe_pf [22] qe_pe [29] qe _pe [27] qe_pf [13] qe_pf [14] qe_pb [27] ov dd w y aa ab ac ad ae af ag ah r t u v 1 14 13 12 11 10 98765432 detail c
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ball layout diagrams freescale semiconductor 8 the following figure provides detailed view d of the mpc8569e 783-pin bga ball map diagram. figure 6. mpc8569e detail d ball map gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v dd v dd v dd v dd v dd v dd v dd v dd gnd gnd v dd v dd v dd v dd v dd v dd gnd gnd bv dd irq [0] irq5_ msrcid [4] irq6_ dval xv dd xgnd irq [3] irq [2] score- v dd score- gnd gnd irq [1] rsvd sd_tx [0] sd_tx [0] score- gnd score- v dd sd_rx [0] sd_rx [0] rsvd rsvd gnd xv dd xgnd agnd_ srds avdd_ srds score- gnd score- v dd gnd xv dd xgnd sd_tx [1] sd_tx [1] score- gnd score- v dd sd_rx [1] sd_rx [1] gnd sd_pll_ tpd sd_imp_ cal_rx xgnd xv dd sd_ref_ clk sd_ref_ clk score- v dd score- gnd gnd xgnd xv dd sd_tx [2] sd_tx [2] score- v dd score- gnd sd_rx [2] sd_rx [2] ldp [1] lgpl [5] lgpl1_ lfale lgpl4_ lupwait_ lbpbse_ lfrb lgpl0_ lfcle lgpl3_ lfwp sd_tx_ clk xv dd xgnd sd_imp_ cal_tx sd_pll_ tpa score- gnd score- v dd gnd lcs [1] bv dd lcs [0] bv dd la [25] bv dd lcs7_ irq [11] xv dd xgnd sreset hreset_ req score- v dd score- gnd lcs [2] gnd lwe1_ lbs [1] gnd lwe0_ lbs0_ lfwe xv dd xgnd sd_tx [3] sd_tx [3] xgnd score- gnd sd_rx [3] sd_rx [3] la [16] la [17] la [19] la [21] la [23] lgpl2_ loe_ lfre lad [15] lcs6_ irq [10] hreset dma_ dack2_ sd_cmd dma_ ddone_ [0] dma_ dreq2_ sd_dat0 dma_ dack1_ msrcid1 lvdd_ vsel [0] lbctl la [20] la [22] la [24] la [26] lad [13] lad [12] la [27] lcs5_ irq [9] dma_ ddone1_ msrcid2 dma_ dreq1_ msrcid0 gnd ov dd ckstp_ in bv dd lclk [1] bv dd lclk [0] bv dd lad [7] bv dd lad [14] dma_ dack_ [0] ov dd dma_ ddone2_ sd_wp iic2_ scl_sd_ cd uart_ sin0_dma _dack3_ sd_dat2 ckstp_ out gnd lad [2] gnd lad [6] gnd lad [8] gnd lad [11] dma_ dreq_ [0] gnd iic2_ sda_sd_ clk iic1_ scl uart_ cts0_dma _ddone3_ sd_dat3 lsync_ out lsync_ in lad [3] lad [4] lad [5] lale lad [9] lad [10] gnd avdd_ lbiu gnd iic1_ sda lssd_ mode sd_tx_ clk w y aa ab ac ad ae af ag ah r t u v 17 16 15 18 19 20 21 22 23 24 25 26 27 28 detail d uart_ sout0_dma _dreq3_ sd_dat1 uart_ rts [0]
pinout list mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 9 1.2 pinout list the following table provides the pinout listing for the mpc8569e 783 fc-pbga package. table 1. mpc8569e pinout listing signal 1 package pin number pin type power supply note clocks rtc m25 i ov dd ? sysclk p25 i ov dd ? ddr sdram memory interface d1_ma0 e18 o gv dd ? d1_ma1 a18 o gv dd ? d1_ma2 h19 o gv dd ? d1_ma3 g20 o gv dd ? d1_ma4 b18 o gv dd ? d1_ma5 h18 o gv dd ? d1_ma6 c18 o gv dd ? d1_ma7 j21 o gv dd ? d1_ma8 e19 o gv dd ? d1_ma9 g19 o gv dd ? d1_ma10 j18 o gv dd ? d1_ma11 a19 o gv dd ? d1_ma12 j22 o gv dd ? d1_ma13 a15 o gv dd ? d1_ma14 d20 o gv dd ? d1_ma15 c15 o gv dd ? d1_mba0 k17 o gv dd ? d1_mba1 f18 o gv dd ? d1_mba2 e20 o gv dd ? d1_mcas j17 o gv dd ? d1_mck0 e24 o gv dd ? d1_mck0 e23 o gv dd ? d1_mck1 j24 o gv dd ? d1_mck1 j23 o gv dd ? d1_mck2 c20 o gv dd ? d1_mck2 c19 o gv dd ? d1_mcke0 g21 o gv dd ? d1_mcke1 j20 o gv dd ?
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 pinout list freescale semiconductor 10 d1_mcke2 c17 o gv dd ? d1_mcke3 a16 o gv dd ? d1_mcs0 d17 o gv dd ? d1_mcs1 k16 o gv dd ? d1_mcs2 k20 o gv dd ? d1_mcs3 g16 o gv dd ? d1_mdic0 a20 i/o gv dd 27 d1_mdic1 a17 i/o gv dd 27 d1_mdm0 a27 i/o gv dd ? d1_mdm1 e27 i/o gv dd ? d1_mdm2 j27 i/o gv dd ? d1_mdm3 a23 i/o gv dd ? d1_mdm8 e22 i/o gv dd ? d1_mdq0 c28 i/o gv dd ? d1_mdq1 c27 i/o gv dd ? d1_mdq2 c25 i/o gv dd ? d1_mdq3 b25 i/o gv dd ? d1_mdq4 b28 i/o gv dd ? d1_mdq5 a28 i/o gv dd ? d1_mdq6 a26 i/o gv dd ? d1_mdq7 a25 i/o gv dd ? d1_mdq8 g28 i/o gv dd ? d1_mdq9 g27 i/o gv dd ? d1_mdq10 g25 i/o gv dd ? d1_mdq11 f25 i/o gv dd ? d1_mdq12 f28 i/o gv dd ? d1_mdq13 e28 i/o gv dd ? d1_mdq14 e26 i/o gv dd ? d1_mdq15 e25 i/o gv dd ? d1_mdq16 l27 i/o gv dd ? d1_mdq17 l26 i/o gv dd ? d1_mdq18 k23 i/o gv dd ? d1_mdq19 k25 i/o gv dd ? d1_mdq20 k28 i/o gv dd ? d1_mdq21 j28 i/o gv dd ? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
pinout list mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 11 d1_mdq22 j26 i/o gv dd ? d1_mdq23 j25 i/o gv dd ? d1_mdq24 c24 i/o gv dd ? d1_mdq25 c22 i/o gv dd ? d1_mdq26 c21 i/o gv dd ? d1_mdq27 b21 i/o gv dd ? d1_mdq28 b24 i/o gv dd ? d1_mdq29 a24 i/o gv dd ? d1_mdq30 a22 i/o gv dd ? d1_mdq31 a21 i/o gv dd ? d1_mdqs0 d26 i/o gv dd ? d1_mdqs0 c26 i/o gv dd ? d1_mdqs1 h26 i/o gv dd ? d1_mdqs1 g26 i/o gv dd ? d1_mdqs2 k24 i/o gv dd ? d1_mdqs2 l25 i/o gv dd ? d1_mdqs3 d23 i/o gv dd ? d1_mdqs3 c23 i/o gv dd ? d1_mdqs8 h23 i/o gv dd ? d1_mdqs8 g23 i/o gv dd ? d1_mecc0 g24 i/o gv dd ? d1_mecc1 h22 i/o gv dd ? d1_mecc2 g22 i/o gv dd ? d1_mecc3 f21 i/o gv dd ? d1_mecc4 f24 i/o gv dd ? d1_mecc5 d22 i/o gv dd ? d1_mecc6 e21 i/o gv dd ? d1_mecc7 d21 i/o gv dd ? d1_modt0 c16 o gv dd ? d1_modt1 j16 o gv dd ? d1_modt2 g17 o gv dd ? d1_modt3 e16 o gv dd ? d1_mapar_out e15 o gv dd ? d1_mapar_err f15 i gv dd ? d1_mras g18 o gv dd ? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 pinout list freescale semiconductor 12 d1_mwe e17 o gv dd ? d2_ma0 e4 o gv dd ? d2_ma1 a4 o gv dd ? d2_ma2 j7 o gv dd ? d2_ma3 g6 o gv dd ? d2_ma4 b4 o gv dd ? d2_ma5 h4 o gv dd ? d2_ma6 g3 o gv dd ? d2_ma7 j8 o gv dd ? d2_ma8 e5 o gv dd ? d2_ma9 g5 o gv dd ? d2_ma10 j6 o gv dd ? d2_ma11 a5 o gv dd ? d2_ma12 j9 o gv dd ? d2_ma13 d3 o gv dd ? d2_ma14 d6 o gv dd ? d2_ma15 b1 o gv dd ? d2_mba0 j5 o gv dd ? d2_mba1 f4 o gv dd ? d2_mba2 e6 o gv dd ? d2_mcas j4 o gv dd ? d2_mck0 e10 o gv dd ? d2_mck0 e9 o gv dd ? d2_mck1 j11 o gv dd ? d2_mck1 j10 o gv dd ? d2_mck2 c6 o gv dd ? d2_mck2 c5 o gv dd ? d2_mcke0 g7 o gv dd ? d2_mcke1 k8 o gv dd ? d2_mcke2 c2 o gv dd ? d2_mcke3 a2 o gv dd ? d2_mcs0 e3 o gv dd ? d2_mcs1 a6 o gv dd ? d2_mcs2 h7 o gv dd ? d2_mcs3 g2 o gv dd ? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
pinout list mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 13 d2_mdic0 j2 i/o gv dd 27 d2_mdic1 l2 i/o gv dd 27 d2_mdm0/d1_mdm4 a13 i/o gv dd ? d2_mdm1/d1_mdm5 d13 i/o gv dd ? d2_mdm2/d1_mdm6 g14 i/o gv dd ? d2_mdm3/d1_mdm7 a9 i/o gv dd ? d2_mdm8 e8 i/o gv dd ? d2_mdq0/d1_mdq32 b14 i/o gv dd ? d2_mdq1/d1_mdq33 c14 i/o gv dd ? d2_mdq2/d1_mdq34 c11 i/o gv dd ? d2_mdq3/d1_mdq35 b11 i/o gv dd ? d2_mdq4/d1_mdq36 b15 i/o gv dd ? d2_mdq5/d1_mdq37 a14 i/o gv dd ? d2_mdq6/d1_mdq38 a12 i/o gv dd ? d2_mdq7/d1_mdq39 a11 i/o gv dd ? d2_mdq8/d1_mdq40 f14 i/o gv dd ? d2_mdq9/d1_mdq41 f13 i/o gv dd ? d2_mdq10/d1_mdq42 g11 i/o gv dd ? d2_mdq11/d1_mdq43 f11 i/o gv dd ? d2_mdq12/d1_mdq44 e14 i/o gv dd ? d2_mdq13/d1_mdq45 d14 i/o gv dd ? d2_mdq14/d1_mdq46 d12 i/o gv dd ? d2_mdq15/d1_mdq47 e11 i/o gv dd ? d2_mdq16/d1_mdq48 j15 i/o gv dd ? d2_mdq17/d1_mdq49 j14 i/o gv dd ? d2_mdq18/d1_mdq50 k13 i/o gv dd ? d2_mdq19/d1_mdq51 j12 i/o gv dd ? d2_mdq20/d1_mdq52 h15 i/o gv dd ? d2_mdq21/d1_mdq53 g15 i/o gv dd ? d2_mdq22/d1_mdq54 g13 i/o gv dd ? d2_mdq23/d1_mdq55 h12 i/o gv dd ? d2_mdq24/d1_mdq56 c10 i/o gv dd ? d2_mdq25/d1_mdq57 c8 i/o gv dd ? d2_mdq26/d1_mdq58 c7 i/o gv dd ? d2_mdq27/d1_mdq59 b7 i/o gv dd ? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 pinout list freescale semiconductor 14 d2_mdq28/d1_mdq60 b10 i/o gv dd ? d2_mdq29/d1_mdq61 a10 i/o gv dd ? d2_mdq30/d1_mdq62 a8 i/o gv dd ? d2_mdq31/d1_mdq63 a7 i/o gv dd ? d2_mdqs0/d1_mdqs4 c12 i/o gv dd ? d2_mdqs0 /d1_mdqs4 c13 i/o gv dd ? d2_mdqs1/d1_mdqs5 g12 i/o gv dd ? d2_mdqs1 /d1_mdqs5 f12 i/o gv dd ? d2_mdqs2/d1_mdqs6 j13 i/o gv dd ? d2_mdqs2 /d1_mdqs6 k14 i/o gv dd ? d2_mdqs3/d1_mdqs7 d9 i/o gv dd ? d2_mdqs3 /d1_mdqs7 c9 i/o gv dd ? d2_mdqs8 h9 i/o gv dd ? d2_mdqs8 g9 i/o gv dd ? d2_mecc0 g10 i/o gv dd ? d2_mecc1 h8 i/o gv dd ? d2_mecc2 g8 i/o gv dd ? d2_mecc3 f7 i/o gv dd ? d2_mecc4 f10 i/o gv dd ? d2_mecc5 d8 i/o gv dd ? d2_mecc6 e7 i/o gv dd ? d2_mecc7 d7 i/o gv dd ? d2_modt0 c1 o gv dd ? d2_modt1 a3 o gv dd ? d2_modt2 h3 o gv dd ? d2_modt3 e1 o gv dd ? d2_mapar_out f1 o gv dd ? d2_mapar_err g1 i gv dd ? d2_mras g4 o gv dd ? d2_mwe e2 o gv dd ? dma dma_dack0 af23 o ov dd 2 dma_dack1 /msrcid1 ad27 o ov dd 11 dma_dack2 /sd_cmd ad24 o ov dd ? dma_ddone0 ad25 o ov dd 2 table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
pinout list mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 15 dma_ddone1 /msrcid2 ae24 o ov dd 2 dma_ddone2 /sd_wp af25 o ov dd ? dma_dreq0 ag23 i ov dd ? dma_dreq1 /msrcid0 ae25 i ov dd ? dma_dreq2 /sd_dat0 ad26 i ov dd ? duart uart_sout0/dma_dreq3 /sd_dat1 ag28 o ov dd 2 uart_sin0/dma_dack3 /sd_dat2 af27 i ov dd ? uart_cts0 /dma_ddone3 /sd_dat3 ag27 i ov dd ? uart_rts0 ah28 o ov dd ? enhanced local bus co ntroller interface la16 ad15 o bv dd 2 la17 ad16 o bv dd 2 la18 ae14 o bv dd 2 la19 ad17 o bv dd 2 la20 ae16 o bv dd 2 la21 ad18 o bv dd 2 la22 ae17 o bv dd 11 la23 ad19 o bv dd 2 la24 ae18 o bv dd 18 la25 ac20 o bv dd 18 la26 ae19 o bv dd 18 la27 ae22 o bv dd 18 lad0 ag14 i/o bv dd 23 lad1 af14 i/o bv dd 23 lad2 ag16 i/o bv dd 23 lad3 ah17 i/o bv dd 23 lad4 ah18 i/o bv dd 23 lad5 ah19 i/o bv dd 23 lad6 ag18 i/o bv dd 23 lad7 af20 i/o bv dd 23 lad8 ag20 i/o bv dd 23 lad9 ah21 i/o bv dd 23 lad10 ah22 i/o bv dd 23 lad11 ag22 i/o bv dd 23 table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 pinout list freescale semiconductor 16 lad12 ae21 i/o bv dd 23 lad13 ae20 i/o bv dd 23 lad14 af22 i/o bv dd 23 lad15 ad21 i/o bv dd 23 lale ah20 o bv dd 20 lbctl ae15 o bv dd 20 lclk0 af18 o bv dd 11 lclk1 af16 o bv dd 11 lcs0 ac18 o bv dd 2 lcs1 ac16 o bv dd 2 lcs2 ab16 o bv dd 2 lcs3 ac14 o bv dd 21 lcs4 /irq8 ad14 i/o bv dd 21 lcs5 /irq9 ae23 i/o bv dd 21 lcs6 /irq10 ad22 i/o bv dd 21 lcs7 /irq11 ac22 i/o bv dd 21 ldp0 ab14 i/o bv dd ? ldp1 aa15 i/o bv dd ? lgpl0/lfcle aa19 o bv dd 2 lgpl1/lfale aa17 o bv dd 2 lgpl2/loe /lfre ad20 o bv dd 20 lgpl3/lfwp aa20 o bv dd 2 lgpl4/lupwait/lbpbse/lfrb aa18 i/o bv dd 29 lgpl5 aa16 o bv dd 2 lsync_in ah16 i bv dd ? lsync_out ah15 o bv dd ? lwe0 /lbs0 lfwe ab20 o bv dd 11 lwe1 /lbs1 ab18 o bv dd 24 i 2 c iic1_sda ah26 i/o ov dd 5, 28 iic1_scl ag26 i/o ov dd 5, 28 iic2_sda/sd_clk ag25 i/o ov dd 3 iic2_scl/sd_cd af26 i/o ov dd 3 jtag tck n21 i ov dd ? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
pinout list mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 17 tdi p21 i ov dd 26 tdo p23 o ov dd 25 tms n22 i ov dd 26 trst p22 i ov dd 26 programmable interrupt controller irq0 r20 i ov dd ? irq1 t21 i ov dd ? irq2 r26 i ov dd ? irq3 r25 i ov dd ? irq4/msrcid3 n20 i ov dd ? irq5/msrcid4 r21 i ov dd ? irq6/mdval r22 i ov dd ? irq_out m20 o ov dd 5, 6, 11 mcp m22 i ov dd 6 ude m21 i ov dd 6 quicc engine block qe_pa0 t11 i/o lv dd 1? qe_pa1 u11 i/o lv dd 1? qe_pa2 r11 i/o lv dd 1? qe_pa3 u10 i/o lv dd 1? qe_pa4 r10 i/o lv dd 1? qe_pa5 v11 i/o ov dd ? qe_pa6 r9 i/o lv dd 1? qe_pa7 u9 i/o lv dd 1? qe_pa8 t8 i/o lv dd 1? qe_pa9 u8 i/o lv dd 1? qe_pa10 v10 i/o ov dd ? qe_pa11 v9 i/o ov dd ? qe_pa12 r8 i/o lv dd 1? qe_pa13 v8 i/o ov dd ? qe_pa14 p7 i/o lv dd 2? qe_pa15 l6 i/o lv dd 2? qe_pa16 m6 i/o lv dd 2? qe_pa17 n6 i/o lv dd 2? qe_pa18 l5 i/o lv dd 2? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 pinout list freescale semiconductor 18 qe_pa19 p1 i/o ov dd ? qe_pa20 m5 i/o lv dd 2? qe_pa21 n5 i/o lv dd 2? qe_pa22 l4 i/o lv dd 2? qe_pa23 m4 i/o lv dd 2? qe_pa24 n1 i/o ov dd ? qe_pa25 r1 i/o ov dd ? qe_pa26 n4 i/o lv dd 2? qe_pa27 t1 i/o ov dd ? qe_pa28 n2 i/o ov dd ? qe_pa29 p6 i/o lv dd 1? qe_pa30 u6 i/o lv dd 1? qe_pa31 t5 i/o lv dd 1? qe_pb0 r5 i/o lv dd 1? qe_pb1 p5 i/o lv dd 1? qe_pb2 v6 i/o ov dd ? qe_pb3 t3 i/o lv dd 1? qe_pb4 u3 i/o lv dd 1? qe_pb5 u4 i/o lv dd 1? qe_pb6 u5 i/o lv dd 1? qe_pb7 v3 i/o ov dd 11 qe_pb8 v4 i/o ov dd ? qe_pb9 p4 i/o lv dd 1? qe_pb10 v5 i/o ov dd ? qe_pb11 w11 i/o ov dd ? qe_pb12 l11 i/o lv dd 2? qe_pb13 m11 i/o lv dd 2? qe_pb14 n11 i/o lv dd 2? qe_pb15 p11 i/o lv dd 2? qe_pb16 p10 i/o lv dd 2? qe_pb17 p2 i/o ov dd ? qe_pb18 l10 i/o lv dd 2? qe_pb19 m9 i/o lv dd 2? qe_pb20 n9 i/o lv dd 2? qe_pb21 p9 i/o lv dd 2? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
pinout list mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 19 qe_pb22 t2 i/o ov dd ? qe_pb23 r2 i/o ov dd ? qe_pb24 p8 i/o lv dd 2? qe_pb25 u2 i/o ov dd ? qe_pb26 ag13 i/o ov dd 11 qe_pb27 ah14 i/o ov dd 22 qe_pb28 ac8 i/o ov dd 22 qe_pb29 ad8 i/o ov dd ? qe_pb30 ad9 i/o ov dd ? qe_pb31 ad10 i/o ov dd 11 qe_pc0 w3 i/o ov dd ? qe_pc1 w4 i/o ov dd ? qe_pc2 n3 i/o lv dd 2? qe_pc3 l3 i/o lv dd 2? qe_pc4 y7 i/o ov dd 22 qe_pc5 w2 i/o ov dd ? qe_pc6 w5 i/o ov dd ? qe_pc7 w7 i/o ov dd ? qe_pc8 t7 i/o lv dd 1? qe_pc9 r3 i/o lv dd 1? qe_pc10 ab2 i/o ov dd ? qe_pc11 r7 i/o lv dd 1? qe_pc12 aa6 i/o ov dd ? qe_pc13 aa3 i/o ov dd ? qe_pc14 aa5 i/o ov dd ? qe_pc15 aa4 i/o ov dd ? qe_pc16 l7 i/o lv dd 2? qe_pc17 m8 i/o lv dd 2? qe_pc18 ab3 i/o ov dd ? qe_pc19 y5 i/o ov dd ? qe_pc20 u7 i/o lv dd 1? qe_pc21 ab1 i/o ov dd ? qe_pc22 y3 i/o ov dd ? qe_pc23 y4 i/o ov dd ? qe_pc24 n8 i/o lv dd 2? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 pinout list freescale semiconductor 20 qe_pc25 p3 i/o lv dd 1? qe_pc26 w8 i/o ov dd ? qe_pc27 w9 i/o ov dd ? qe_pc28 af13 i/o ov dd ? qe_pc29 v7 i/o ov dd ? qe_pc30 aa14 i/o ov dd ? qe_pc31 aa13 i/o ov dd ? qe_pd0 ah6 i/o ov dd 11 qe_pd1 af6 i/o ov dd ? qe_pd2 ag6 i/o ov dd ? qe_pd3 af5 i/o ov dd ? qe_pd4 ae4 i/o ov dd 22 qe_pd5 ad4 i/o ov dd ? qe_pd6 ab6 i/o ov dd ? qe_pd7 ad7 i/o ov dd ? qe_pd8 ac6 i/o ov dd ? qe_pd9 ad6 i/o ov dd ? qe_pd10 ab5 i/o ov dd ? qe_pd11 ac4 i/o ov dd ? qe_pd12 ae5 i/o ov dd ? qe_pd13 ae6 i/o ov dd ? qe_pd14 ac7 i/o ov dd ? qe_pd15 ab7 i/o ov dd ? qe_pd16 ab8 i/o ov dd ? qe_pd17 aa9 i/o ov dd ? qe_pd18 y8 i/o ov dd ? qe_pd19 aa8 i/o ov dd ? qe_pd20 aa12 i/o ov dd ? qe_pd21 y11 i/o ov dd ? qe_pd22 aa11 i/o ov dd ? qe_pd23 ab11 i/o ov dd ? qe_pd24 aa7 i/o ov dd ? qe_pd25 ab10 i/o ov dd ? qe_pd26 y9 i/o ov dd ? qe_pd27 aa10 i/o ov dd ? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
pinout list mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 21 qe_pd28 af1 i/o ov dd ? qe_pd29 ag1 i/o ov dd ? qe_pd30 ag2 i/o ov dd ? qe_pd31 ah1 i/o ov dd ? qe_pe0 ah2 i/o ov dd ? qe_pe1 ah3 i/o ov dd ? qe_pe2 af4 i/o ov dd ? qe_pe3 ag4 i/o ov dd ? qe_pe4 af3 i/o ov dd ? qe_pe5 ae3 i/o ov dd ? qe_pe6 ag3 i/o ov dd ? qe_pe7 ah5 i/o ov dd ? qe_pe8 ah4 i/o ov dd ? qe_pe9 ag5 i/o ov dd ? qe_pe10 aa1 i/o ov dd ? qe_pe11 y1 i/o ov dd ? qe_pe12 ac1 i/o ov dd ? qe_pe13 ac2 i/o ov dd ? qe_pe14 v1 i/o ov dd ? qe_pe15 ab4 i/o ov dd ? qe_pe16 w1 i/o ov dd ? qe_pe17 v2 i/o ov dd ? qe_pe18 ac3 i/o ov dd ? qe_pe19 ad2 i/o ov dd ? qe_pe20 ad3 i/o ov dd ? qe_pe21 ad1 i/o ov dd ? qe_pe22 u1 i/o ov dd ? qe_pe23 ae1 i/o ov dd ? qe_pe24 ac12 i/o ov dd 11 qe_pe25 ab12 i/o ov dd 2 qe_pe26 ab13 i/o ov dd 11 qe_pe27 ah11 i/o ov dd 19 qe_pe28 ag10 i/o ov dd 19 table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 pinout list freescale semiconductor 22 qe_pe29 ah10 i/o ov dd 19 qe_pe30 ag11 i/o ov dd ? qe_pe31 ae7 i/o ov dd ? qe_pf0 af8 i/o ov dd ? qe_pf1 ag8 i/o ov dd ? qe_pf2 ae8 i/o ov dd ? qe_pf3 ae13 i/o ov dd ? qe_pf4 ac13 i/o ov dd ? qe_pf5 ad13 i/o ov dd ? qe_pf6 af12 i/o ov dd ? qe_pf7 ae12 i/o ov dd ? qe_pf8 ag12 i/o ov dd ? qe_pf9 ad12 i/o ov dd 2 qe_pf10 ac10 i/o ov dd 2 qe_pf11 ac11 i/o ov dd 2 qe_pf12 ad11 i/o ov dd ? qe_pf13 ah12 i/o ov dd 11 qe_pf14 ah13 i/o ov dd 2 qe_pf15 ae10 i/o ov dd ? qe_pf16 ae9 i/o ov dd ? qe_pf17 af9 i/o ov dd ? qe_pf18 af10 i/o ov dd ? qe_pf19 ah8 i/o ov dd ? qe_pf20 ah7 i/o ov dd ? qe_pf21 ag9 i/o ov dd ? qe_pf22 ah9 i/o ov dd ? serdes sd_imp_cal_rx w22 i ? 7 sd_imp_cal_tx aa25 i ? 17 sd_pll_tpa aa26 o av dd _srds 8 sd_pll_tpd w21 o xv dd 8 sd_ref_clk w26 i scorevdd ? sd_ref_clk w25 i scorevdd ? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
pinout list mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 23 sd_rx0 t28 i scorevdd 30 sd_rx0 t27 i scorevdd 30 sd_rx1 v28 i scorevdd 30 sd_rx1 v27 i scorevdd 30 sd_rx2 y28 i scorevdd 30 sd_rx2 y27 i scorevdd 30 sd_rx3 ab28 i scorevdd 30 sd_rx3 ab27 i scorevdd 30 sd_tx0 t23 o xv dd 31 sd_tx0 t24 o xv dd 31 sd_tx1 v23 o xv dd 31 sd_tx1 v24 o xv dd 31 sd_tx2 y23 o xv dd 31 sd_tx2 y24 o xv dd 31 sd_tx3 ab23 o xv dd 31 sd_tx3 ab24 o xv dd 31 sd_tx_clk aa21 o xv dd 8 sd_tx_clk aa22 o xv dd 8 system control ckstp_in ae28 i ov dd 4 ckstp_out af28 o ov dd 5, 6, 11 hreset ad23 i ov dd 4 hreset_req ac26 o ov dd 11 sreset ac25 i ov dd 4 debug trig_out/ready/quiesce p24 o ov dd 11 clk_out m24 o ov dd ? trig_in n25 i ov dd ? voltag e control lvdd_vsel0 ad28 i ov dd 15 lvdd_vsel1 p26 i ov dd 16 bvdd_vsel0 n26 i ov dd 14 bvdd_vsel1 p20 i ov dd 14 design for test lssd_mode ah27 i ov dd 10 table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 pinout list freescale semiconductor 24 power management asleep m23 o ov dd 11 thermal management reserved u21 ? ? 9 reserved u20 ? ? 9 reserved t22 ? ? 9 analog d1_mvref n27 reference voltage for ddr mv ref ? d2_mvref j1 ? power and ground v dd l13 1.0-v/1.1-v core power supply v dd ? v dd l17 1.0-v/1.1-v core power supply v dd ? v dd l19 1.0-v/1.1-v core power supply v dd ? v dd m12 1.0-v/1.1-v core power supply v dd ? v dd m14 1.0-v/1.1-v core power supply v dd ? v dd m16 1.0-v/1.1-v core power supply v dd ? v dd m18 1.0-v/1.1-v core power supply v dd ? v dd n13 1.0-v/1.1-v core power supply v dd ? v dd n15 1.0-v/1.1-v core power supply v dd ? v dd n17 1.0-v/1.1-v core power supply v dd ? v dd n19 1.0-v/1.1-v core power supply v dd ? v dd p12 1.0-v/1.1-v core power supply v dd ? v dd p16 1.0-v/1.1-v core power supply v dd ? v dd p18 1.0-v/1.1-v core power supply v dd ? v dd r13 1.0-v/1.1-v core power supply v dd ? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
pinout list mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 25 v dd r15 1.0-v/1.1-v core power supply v dd ? v dd r17 1.0-v/1.1-v core power supply v dd ? v dd r19 1.0-v/1.1-v core power supply v dd ? v dd t12 1.0-v/1.1-v core power supply v dd ? v dd t14 1.0-v/1.1-v core power supply v dd ? v dd t16 1.0-v/1.1-v core power supply v dd ? v dd t18 1.0-v/1.1-v core power supply v dd ? v dd u13 1.0-v/1.1-v core power supply v dd ? v dd u15 1.0-v/1.1-v core power supply v dd ? v dd u17 1.0-v/1.1-v core power supply v dd ? v dd u19 1.0-v/1.1-v core power supply v dd ? v dd v12 1.0-v/1.1-v core power supply v dd ? v dd v14 1.0-v/1.1-v core power supply v dd ? v dd v16 1.0-v/1.1-v core power supply v dd ? v dd v18 1.0-v/1.1-v core power supply v dd ? v dd w13 1.0-v/1.1-v core power supply v dd ? v dd w15 1.0-v/1.1-v core power supply v dd ? v dd w17 1.0-v/1.1-v core power supply v dd ? v dd w19 1.0-v/1.1-v core power supply v dd ? v dd y12 1.0-v/1.1-v core power supply v dd ? v dd y14 1.0-v/1.1-v core power supply v dd ? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 pinout list freescale semiconductor 26 v dd y18 1.0-v/1.1-v core power supply v dd ? bv dd ac15 3.3-/2.5-/1.8-v enhanced local bus controller (elbc) power supply bv dd ? bv dd ac17 3.3-/2.5-/1.8-v enhanced local bus controller (elbc) power supply bv dd ? bv dd ac19 3.3-/2.5-/1.8-v enhanced local bus controller (elbc) power supply bv dd ? bv dd ac21 3.3-/2.5-/1.8-v enhanced local bus controller (elbc) power supply bv dd ? bv dd af15 3.3-/2.5-/1.8-v enhanced local bus controller (elbc) power supply bv dd ? bv dd af17 3.3-/2.5-/1.8-v enhanced local bus controller (elbc) power supply bv dd ? bv dd af19 3.3-/2.5-/1.8-v enhanced local bus controller (elbc) power supply bv dd ? bv dd af21 3.3-/2.5-/1.8-v enhanced local bus controller (elbc) power supply bv dd ? gv dd b12 1.8-/1.5-v ddr power supply gv dd ? gv dd b16 1.8-/1.5-v ddr power supply gv dd ? gv dd b19 1.8-/1.5-v ddr power supply gv dd ? gv dd b2 1.8-/1.5-v ddr power supply gv dd ? gv dd b22 1.8-/1.5-v ddr power supply gv dd ? gv dd b26 1.8-/1.5-v ddr power supply gv dd ? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
pinout list mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 27 gv dd b5 1.8-/1.5-v ddr power supply gv dd ? gv dd b8 1.8-/1.5-v ddr power supply gv dd ? gv dd c3 1.8-/1.5-v ddr power supply gv dd ? gv dd d1 1.8-/1.5-v ddr power supply gv dd ? gv dd d10 1.8-/1.5-v ddr power supply gv dd ? gv dd d15 1.8-/1.5-v ddr power supply gv dd ? gv dd d18 1.8-/1.5-v ddr power supply gv dd ? gv dd d24 1.8-/1.5-v ddr power supply gv dd ? gv dd d27 1.8-/1.5-v ddr power supply gv dd ? gv dd d4 1.8-/1.5-v ddr power supply gv dd ? gv dd e12 1.8-/1.5-v ddr power supply gv dd ? gv dd f16 1.8-/1.5-v ddr power supply gv dd ? gv dd f19 1.8-/1.5-v ddr power supply gv dd ? gv dd f2 1.8-/1.5-v ddr power supply gv dd ? gv dd f22 1.8-/1.5-v ddr power supply gv dd ? gv dd f26 1.8-/1.5-v ddr power supply gv dd ? gv dd f5 1.8-/1.5-v ddr power supply gv dd ? gv dd f8 1.8-/1.5-v ddr power supply gv dd ? gv dd h10 1.8-/1.5-v ddr power supply gv dd ? gv dd h13 1.8-/1.5-v ddr power supply gv dd ? gv dd h16 1.8-/1.5-v ddr power supply gv dd ? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 pinout list freescale semiconductor 28 gv dd h2 1.8-/1.5-v ddr power supply gv dd ? gv dd h20 1.8-/1.5-v ddr power supply gv dd ? gv dd h24 1.8-/1.5-v ddr power supply gv dd ? gv dd h27 1.8-/1.5-v ddr power supply gv dd ? gv dd h5 1.8-/1.5-v ddr power supply gv dd ? gv dd j19 1.8-/1.5-v ddr power supply gv dd ? gv dd j3 1.8-/1.5-v ddr power supply gv dd ? gv dd k10 1.8-/1.5-v ddr power supply gv dd ? gv dd k11 1.8-/1.5-v ddr power supply gv dd ? gv dd k18 1.8-/1.5-v ddr power supply gv dd ? gv dd k22 1.8-/1.5-v ddr power supply gv dd ? gv dd k26 1.8-/1.5-v ddr power supply gv dd ? gv dd k3 1.8-/1.5-v ddr power supply gv dd ? gv dd k4 1.8-/1.5-v ddr power supply gv dd ? gv dd k6 1.8-/1.5-v ddr power supply gv dd ? gv dd k9 1.8-/1.5-v ddr power supply gv dd ? gv dd l15 1.8-/1.5-v ddr power supply gv dd ? gv dd l21 1.8-/1.5-v ddr power supply gv dd ? gv dd l23 1.8-/1.5-v ddr power supply gv dd ? lv dd 1 r4 3.3-/2.5-v ethernet power supply lv dd 1? lv dd 1 r6 3.3-/2.5-v ethernet power supply lv dd 1? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
pinout list mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 29 lv dd 1 t10 3.3-/2.5-v ethernet power supply lv dd 1? lv dd 2 m10 3.3-/2.5-v ethernet power supply lv dd 2? lv dd 2 m3 3.3-/2.5-v ethernet power supply lv dd 2? lv dd 2 m7 3.3-/2.5-v ethernet power supply lv dd 2? ov dd ab9 3.3-v power supply ov dd ? ov dd ac5 3.3-v power supply ov dd ? ov dd ae11 3.3-v power supply ov dd ? ov dd ae2 3.3-v power supply ov dd ? ov dd ae27 3.3-v power supply ov dd ? ov dd af24 3.3-v power supply ov dd ? ov dd af7 3.3-v power supply ov dd ? ov dd m26 3.3-v power supply ov dd ? ov dd n23 3.3-v power supply ov dd ? ov dd w10 3.3-v power supply ov dd ? ov dd w6 3.3-v power supply ov dd ? ov dd y2 3.3-v power supply ov dd ? scorevdd aa28 1.0-v/1.1-v serdes power supply scorevdd ? scorevdd ac27 1.0-v/1.1-v serdes power supply scorevdd ? scorevdd r27 1.0-v/1.1-v serdes power supply scorevdd ? scorevdd t25 1.0-v/1.1-v serdes power supply scorevdd ? scorevdd u28 1.0-v/1.1-v serdes power supply scorevdd ? scorevdd v26 1.0-v/1.1-v serdes power supply scorevdd ? scorevdd w27 1.0-v/1.1-v serdes power supply scorevdd ? scorevdd y25 1.0-v/1.1-v serdes power supply scorevdd ? sensevdd p14 core supply sense v dd 13 xv dd aa23 1.0-v/1.1-v serdes i/o power supply xv dd ? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 pinout list freescale semiconductor 30 xv dd ab21 1.0-v/1.1-v serdes i/o power supply xv dd ? xv dd ac24 1.0-v/1.1-v serdes i/o power supply xv dd ? xv dd r23 1.0-v/1.1-v serdes i/o power supply xv dd ? xv dd u23 1.0-v/1.1-v serdes i/o power supply xv dd ? xv dd v21 1.0-v/1.1-v serdes i/o power supply xv dd ? xv dd w24 1.0-v/1.1-v serdes i/o power supply xv dd ? xv dd y22 1.0-v/1.1-v serdes i/o power supply xv dd ? av dd _core l1 1.0-v/1.1-v av dd supply for the core pll ?12 av dd _ddr m28 1.0-v/1.1-v av dd supply for the ddr pll ?12 av dd _lbiu ah24 1.0-v/1.1-v av dd supply for the elbc pll ?12 av dd _plat n28 1.0-v/1.1-v av dd supply for the platform pll ?12 av dd _qe k1 1.0-v/1.1-v av dd supply for the quicc engine block pll ?12 av dd _srds u26 1.0-v/1.1-v av dd supply for the serdes pll ?12 gnd aa2 ? ? ? gnd ab15 ? ? ? gnd ab17 ? ? ? gnd ab19 ? ? ? gnd ac9 ? ? ? gnd ad5 ? ? ? gnd ae26 ? ? ? gnd af11 ? ? ? gnd af2 ? ? ? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
pinout list mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 31 gnd ag15 ? ? ? gnd ag17 ? ? ? gnd ag19 ? ? ? gnd ag21 ? ? ? gnd ag24 ? ? ? gnd ag7 ? ? ? gnd ah23 ? ? ? gnd ah25 ? ? ? gnd b13 ? ? ? gnd b17 ? ? ? gnd b20 ? ? ? gnd b23 ? ? ? gnd b27 ? ? ? gnd b3 ? ? ? gnd b6 ? ? ? gnd b9 ? ? ? gnd c4 ? ? ? gnd d11 ? ? ? gnd d16 ? ? ? gnd d19 ? ? ? gnd d2 ? ? ? gnd d25 ? ? ? gnd d28 ? ? ? gnd d5 ? ? ? gnd e13 ? ? ? gnd f17 ? ? ? gnd f20 ? ? ? gnd f23 ? ? ? gnd f27 ? ? ? gnd f3 ? ? ? gnd f6 ? ? ? gnd f9 ? ? ? gnd h1 ? ? ? gnd h11 ? ? ? gnd h14 ? ? ? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 pinout list freescale semiconductor 32 gnd h17 ? ? ? gnd h21 ? ? ? gnd h25 ? ? ? gnd h28 ? ? ? gnd h6 ? ? ? gnd k12 ? ? ? gnd k15 ? ? ? gnd k19 ? ? ? gnd k2 ? ? ? gnd k21 ? ? ? gnd k27 ? ? ? gnd k5 ? ? ? gnd k7 ? ? ? gnd l12 ? ? ? gnd l14 ? ? ? gnd l16 ? ? ? gnd l18 ? ? ? gnd l20 ? ? ? gnd l22 ? ? ? gnd l24 ? ? ? gnd l28 ? ? ? gnd l8 ? ? ? gnd l9 ? ? ? gnd m1 ? ? ? gnd m13 ? ? ? gnd m15 ? ? ? gnd m17 ? ? ? gnd m19 ? ? ? gnd m2 ? ? ? gnd m27 ? ? ? gnd n10 ? ? ? gnd n12 ? ? ? gnd n14 ? ? ? gnd n16 ? ? ? gnd n18 ? ? ? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
pinout list mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 33 gnd n24 ? ? ? gnd n7 ? ? ? gnd p13 ? ? ? gnd p17 ? ? ? gnd p19 ? ? ? gnd p27 ? ? ? gnd p28 ? ? ? gnd r12 ? ? ? gnd r14 ? ? ? gnd r16 ? ? ? gnd r18 ? ? ? gnd t13 ? ? ? gnd t15 ? ? ? gnd t17 ? ? ? gnd t19 ? ? ? gnd t4 ? ? ? gnd t6 ? ? ? gnd t9 ? ? ? gnd u12 ? ? ? gnd u14 ? ? ? gnd u16 ? ? ? gnd u18 ? ? ? gnd u22 ? ? ? gnd v13 ? ? ? gnd v15 ? ? ? gnd v17 ? ? ? gnd v19 ? ? ? gnd w12 ? ? ? gnd w14 ? ? ? gnd w16 ? ? ? gnd w18 ? ? ? gnd y6 ? ? ? gnd y10 ? ? ? gnd y13 ? ? ? gnd y15 ? ? ? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 pinout list freescale semiconductor 34 gnd y16 ? ? ? gnd y17 ? ? ? gnd y19 ? ? ? gnd v20 ? ? ? gnd t20 ? ? ? gnd w20 ? ? ? gnd y20 ? ? ? sensevss p15 ground sense ? 13 scoregnd aa27 serdes core logic gnd ?? scoregnd ab26 serdes core logic gnd ?? scoregnd ac28 serdes core logic gnd ?? scoregnd r28 serdes core logic gnd ?? scoregnd t26 serdes core logic gnd ?? scoregnd u27 serdes core logic gnd ?? scoregnd v25 serdes core logic gnd ?? scoregnd w28 serdes core logic gnd ?? scoregnd y26 serdes core logic gnd ?? xgnd aa24 serdes transceiver pad gnd ?? xgnd ab22 serdes transceiver pad gnd ?? xgnd ab25 serdes transceiver pad gnd ?? xgnd ac23 serdes transceiver pad gnd ?? xgnd r24 serdes transceiver pad gnd ?? xgnd u24 serdes transceiver pad gnd ?? xgnd v22 serdes transceiver pad gnd ?? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
pinout list mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 35 xgnd w23 serdes transceiver pad gnd ?? xgnd y21 serdes transceiver pad gnd ?? agnd_srds u25 serdes pll gnd ? ? notes: 1. all multiplexed signals are listed only once and do not reoccur. 2. this pin is a reset configuration pin. it has a weak internal pull-up p-fet which is enabled only when the processor is in th e reset state. this pull-up is designed such that it can be overpowered by an external 4.7-k pull-down resistor. however, if the signal is intended to be high after reset, and if there is any de vice on the net which might pull down the value of the net at reset, then a pull-up or active driver is needed. 3. when configured as i2c, this pin is an open drain signal and recommend a pull-up resistor (1 k ) be placed on this pin to ov dd . when configured as sd, this pin is not open drain and does not require a pull-up. 4. this pin has a weak internal pull-up resistor (~20 k ). 5. this pin is an open drain signal. 6. recommend a weak pull-up resistor (2?10 k ) be placed on this pin to ov dd . 7. this pin requires a 200- pull-down to ground. 8. do not connect. 9. recommend a weak pull-down resistor (2?10 k ) be placed on this pin to gnd. 10. these are test signals for factory use only and must be pulled up (100 ?1 k ) to ov dd for normal machine operation. 11. these pins must not be pulled down during power-on reset. 12. see an4232 mpc8569e powerquicc iii design checklist for the required pll filters to be attached to the av dd pin. 13. these pins are connected to the v dd /gnd planes internally and may be used by the core power supply to improve tracking and regulation. 14. this pin selects the voltage of elbc interface (bv dd ). this pin has internal weak pull down. 15. this pin selects the voltage of ucc1 and ucc3 interfaces (lv dd 1). this pin has internal weak pull down. 16. this pin selects the voltage of ucc2 and ucc4 interfaces (lv dd 2). this pin has internal weak pull down. 17. this pin requires a 100- pull down to ground. 18. the value of la[2 4:27] during reset sets the ccb clock to sysclk pll ratio. these pins require 4.7-k pull-up or pull-down resistors. see an4232 mpc8569e powerquicc iii design checklist for more details. 19. the value of qe_pe[27:29] during reset sets th e ddr clock pll settings. these pins require 4.7-k pull up or pull down resistors. see an4232 mpc8569e powerquicc iii design checklist for more details. 20. the value of lale, lgpl2 / loe /lfre and lbctl at reset set the e500 core clock to ccb clock pll ratio. these pins require 4.7-k pull-up or pull-down resistors. see the an4232 mpc8569e powerquicc iii design checklist for more details. 21. the value of lcs [3:7] at reset sets the qe pll settings. these pins require 4.7-k pull up or pull down resistors. see an4232 mpc8569e powerquicc iii design checklist for more details. 22. the value of qe_pb[27:28], qe_pc4 and qe_pd4 at rese t sets the boot rom location. these pins require 4.7-k pull up or pull down resistors. see the mpc8569e powerquicc iii integrated host pr ocessor family reference manual for details 23. these pins are sampled at reset for gener al-purpose configuration use by software. the value of lad[0:15] at reset sets the upper 16 bits of the gpporcr 24. these pins must not be pulled up during power-on reset. 25. this output is actively driven during reset rather than being three-stated during reset. table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 overall dc electrical characteristics freescale semiconductor 36 2 electrical characteristics this section provides the ac and dc electrical specifications for the mpc8569e. this device is currently targeted to these specifications, some of which are independent of the i/o cell, but are included for a more comp lete reference. these are not purely i/o buffer design specifications. 2.1 overall dc electrical characteristics this section covers the dc ratings, conditions, and other characteristics. 2.1.1 absolute maximum ratings the following table provides the absolute maximum ratings. 26. these jtag pins have weak internal pull-up p-fets that are always enabled. 27. when operating in ddr2 mode, connect dn_mdic[0] to ground through an 18.2- (full-strength mode) or 36.4- (half-strength mode) precision 1% resistor and connect dn_mdic[1] to gv dd through an 18.2- (full-strength mode) or 36.4- (half-strength mode) precisi on 1% resistor. when operating in ddr3 mode, connect dn_mdic[0] to ground through a 20- (full-strength mode) or 40.2- (half-strength mode) precision 1% resistor and connect dn_mdic[1] to gv dd through a 20- (full-strength mode) or 40.2- (half-strength mode) precision 1% resistor. these pins are used for automatic calibration of the ddr ios. 28. recommend a pull-up resistor (1 k ) to be placed on this pin to ov dd . 29. for systems which boot from local bus (gpcm)-controlled nor flash or (fc m)-controlled nand flash, a pull up on lgpl4 is required. 30. if unused, these pins must be connected to gnd. 31. if unused, these pins must be left unconnected. table 2. absolute maximum ratings 1 characteristic symbol range unit notes core supply voltage v dd ?0.3 to 1.21 v ? pll supply voltage av dd _core av dd _ddr, av dd _lbiu, av dd _plat, av dd _qe, av dd _srds ?0.3 to 1.21 v ? core power supply for serdes transceiver scorevdd ?0.3 to 1.21 v ? pad power supply for serdes transceiver xv dd ?0.3 to 1.21 v ? ddr2 and ddr3 dram i/o voltage gv dd ?0.3 to 1.98 ?0.3 to 1.65 v2 quicc engine block ethernet interface i/o voltage lv dd 1 ?0.3 to 3.63 ?0.3 to 2.75 v? quicc engine block ethernet interface i/o voltage lv dd 2 ?0.3 to 3.63 ?0.3 to 2.75 v? table 1. mpc8569e pinout listing (continued) signal 1 package pin number pin type power supply note
overall dc electrica l characteristics mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 37 2.1.1.1 recommended operating conditions the following table provides the recomm ended operating conditions for this device. proper device operation outside these conditions is not guaranteed. debug, dma, duart, pic, i 2 c, jtag, power management, quicc engine block, esdhc, gpio, clocking, spi, i/o voltage select and system control i/o voltage ov dd ?0.3 to 3.63 v ? enhanced local bus i/o voltage bv dd ?0.3 to 3.63 ?0.3 to 2.75 ?0.3 to 1.98 v? input voltage ddr2/ddr3 dram signals mv in ?0.3 to (gv dd + 0.3) v 2, 3 ddr2/ddr3 dram reference mv ref ?0.3 to (gv dd + 0.3) v ? ethernet signals lv in ?0.3 to (lv dd n + 0.3) v 3 enhanced local bus signals bv in ?0.3 to (bv dd + 0.3) ? 3 debug, dma, duart, pic, i 2 c, jtag, power management, quicc engine block, esdhc, gpio, clocking, spi, i/o voltage select and system control i/o voltage ov in ?0.3 to (ov dd + 0.3) v 3 serdes signals xv in ?0.3 to (xv dd + 0.3) v ? storage junction temperature range t stg ?55 to 150 c? notes: 1. functional and tested operating conditions are given in ta b l e 3 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresse s beyond those listed may affect device reliability or cause permanent damage to the device. 2. the ?0.3 to 1.98 v range is for ddr2, and the ?0.3 to 1.65 v range is for ddr3. 3. caution: (b,m,l,o,x)v in must not exceed (b,g,l,o,x)v dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. table 3. recommended operating conditions characteristic symbol recommended value unit notes core supply voltage v dd 1.0 v 30 mv 1.1 v 33 mv v1 pll supply voltage av dd _core, av dd _ddr, av dd _lbiu, av dd _plat, av dd _qe, av dd _srds 1.0 v 30 mv 1.1 v 33 mv v2 core power supply for serdes transceiver scorevdd 1.0 v 30 mv 1.1 v 33 mv v1 table 2. absolute maximum ratings 1 (continued) characteristic symbol range unit notes
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 overall dc electrical characteristics freescale semiconductor 38 pad power supply for serdes transceiver xv dd 1.0 v 30 mv 1.1 v 33 mv v1 ddr2 and ddr3 dram i/o voltage gv dd 1.8 v 90 mv 1.5 v 75 mv v4 quicc engine block ethernet interface i/o voltage lv dd 1 3.3 v 165 mv 2.5 v 125 mv v? quicc engine block ethernet interface i/o voltage lv dd 2 3.3 v 165 mv 2.5 v 125 mv v? debug, dma, duart, pic, i 2 c, jtag, power management, quicc engine block, esdhc, gpio, clocking, spi, i/o voltage select and system control i/o voltage ov dd 3.3 v 165 mv v ? enhanced local bus i/o voltage bv dd 3.3 v 165 mv 2.5 v 125 mv 1.8 v 90 mv v? input voltage ddr2 and ddr3 dram signals mv in gnd to gv dd v3 ddr2 dram reference mv ref gv dd /2 2% v 3 ddr3 dram reference mv ref gv dd /2 1% v 3 ethernet signals lv in gnd to lv dd n v3 enhanced local bus signals bv in gnd to bv dd v3 debug, dma, duart, pic, i 2 c, jtag, power management, quicc engine, esdhc, gpio, clocking, spi, i/o voltage select and system control i/o voltage ov in gnd to ov dd v3 serdes signals xv in gnd to xv dd v? operating temperature range commercial t a , t j t a = 0 (min) to t j = 105 (max) o c? notes : 1. a nominal voltage of 1.1 v is recommended for cpu speeds of 1.33 ghz and quicc engine block speeds of 667 mhz. 2. this voltage is the input to the filter and not the voltage at the av dd pin, which may be reduced from v dd by the filter. 3. caution: (b,m,l,o,x)v in must not exceed (b,g,l,o,x)v dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. the 1.8 v 90 mv range is for ddr2, and the 1.5 v 75 mv range is for ddr3. table 3. recommended operating conditions (continued) characteristic symbol recommended value unit notes
overall dc electrica l characteristics mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 39 the following figure shows the undershoot and overs hoot voltages at the in terfaces of the mpc8569e. figure 7. overshoot/undershoot voltage for bv dd /gv dd /lv dd /ov dd /xv dd the core voltage must always be prov ided at nominal 1.0 or 1.1 v. see table 3 for actual recommended core voltage. voltage to the processor interface i/os is provided through separate sets of supply pins and must be provided at the voltages shown in table 3 . the input voltage threshold scales with respect to the associated i/o supply voltage. (b,m,l,o)v dd based receivers are simple cmos i/o circuits and satis fy appropriate lvcmos type specifica tions. the ddr2 and ddr3 sdram interface uses differential receivers refere nced by the externally supplied d n_ mvref signal (nominally set to gv dd /2) as is appropriate for the sstl_1.8 electrical sign aling standard for ddr2 or 1.5-v electrical signaling for ddr3. the ddr dqs receivers cannot be operated in single-ended fashion. the complement signal must be properly driven and cannot be grounded. gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% nominal (b,g,l,o,x)v dd + 20% (b,g,l,o,x)v dd (b,g,l,o,x)v dd + 5% of t clock 1 1. note that t clock refers to the clock period associated with the respective interface: v ih v il note: for ddr, t clock references dn_mck. for elbc, t clock references lclkn for i 2 c and jtag, t clock references sysclk. . for elbc, t clock references lclkn for serdes xv dd , t clock references sd_ref_clk.
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 overall dc electrical characteristics freescale semiconductor 40 2.1.1.2 output driver characteristics the following table provides information on the characteristics of the output driver strengths. the values are preliminary estimates. 2.1.2 power sequencing the mpc8569e requires its power rails to be applied in a sp ecific sequence to ensure proper device operation. these requirements are as follows for power up: 1. v dd , av dd _ n, bv dd , lv dd n , ov dd , scorevdd, xv dd 2. gv dd all supplies must be at their stable values within 50 ms. items on the same line have no ordering requirement with respect to one another. items on separate lines must be ordered sequentially such that volta ge rails on a previous step must reach 90% of th eir value before the voltage rails on the current s tep reach 10% of theirs. note while v dd is ramping, current may be supplied from v dd through the mpc8569e to gv dd . nevertheless, gv dd from an external supply should follow the sequencing described above. from a system standpoint, if any of the i/o power supplies ramp prior to the v dd core supply, the i/os associated with that i/o supply may drive a logic one or zero during power up, and extra current may be drawn by the device. 2.1.3 reset initialization this section describes the ac electrical specifications fo r the reset timing requirements of the mpc8569e. the following table describes the specifications for the reset initialization timing. table 4. output drive capability driver type programmable output impedance ( ) supply voltage notes enhanced local bus interface utilities signals 45 45 45 bv dd = 3.3 v bv dd = 2.5 v bv dd = 1.8 v ? ddr2 signal 18 (full strength mode) 35 (half strength mode) gv dd = 1.8 v 1 ddr3 signal 20 (full strength mode) 40 (half strength mode) gv dd = 1.5 v 1 duart, epic, i 2 c, jtag, system control 45 ov dd = 3.3 v ? note: 1. the drive strength of the ddr2 or ddr3 interface in half-strength mode is at t j = 105 c and at gv dd (min). refer to the mpc8569 reference manual for the ddr impedance programming procedure through the ddr control driver register 1 (ddrcdr_1). table 5. reset initializati on timing sp ecifications parameter min max unit notes required assertion time of hreset 10 ? sysclk 1, 2 minimum assertion time of treset simultaneous to hreset assertion 25 ? ns 3
overall dc electrica l characteristics mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 41 the following table provid es the pll lock times. maximum rise/fall time of hreset ? 1 sysclk 5 minimum assertion time for sreset 3 ? sysclk 4 pll input setup time with stable sysclk before hreset negation 2 ? sysclk ? input setup time for por configurations (other than pll configuration) with respect to negation of hreset 4 ? sysclk 4 input hold time for all por configurations (including pll configuration) with respect to negation of hreset 8 ? sysclk 4 maximum valid-to-high impedance time for actively driven por configurations with respect to negation of hreset ? 5 sysclk 4 note: 1. there may be some extra current leakage when driving signals high during this time. 2. reset assertion timing requirements for ddr3 drams may differ. 3. trst is an asynchronous level sensitive signal. for guidance on how this requirement can be met, refer to the jtag signal termination guidelines in an4232 mpc8569e powerquicc iii design checklist . 4. sysclk is the primary clock input for the mpc8569e. 5. system/board must be designed to ensure the input requirement to the device is achieved. proper device operation is guaranteed for inputs meeting this requ irement by design, simulation, characterization, or functional testing. table 6. pll lock times parameter min max unit core pll lock time ? 100 s platform pll lock time ? 100 s quicc engine block pll lock time ? 100 s ddr pll lock times ? 100 s table 5. reset initialization ti ming specifications (continued) parameter min max unit notes
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 power characteristics freescale semiconductor 42 2.1.4 power-on ramp rate this section describes the ac electrical specifications for the power-on ramp rate requirements. controlling the maximum power-on ramp rate is required to avoid falsely triggering the esd circuitry. the following table provides the power supply ramp rate specifications. 2.2 power characteristics the following table shows the power dissipations of the v dd supply for various operating core complex bus clock (ccb_clk) frequencies versus the core, ddr data rate, and quicc engine bl ock frequencies. note that these numbers are based on design estimates only and are preliminary. more accurate power numbers are available after the measurement on the silicon is complete. table 7. power supply ramp rate parameter min max unit notes required ramp rate for all voltage supplies (including ovdd/cvdd/ gvdd/bvdd/svdd/lvdd, all vdd supplies, mvref and all avdd sup- plies.) ? 36000 v/s 1, 2 note: 1. ramp rate is specified as a linear ramp from 10 to 90%. if non-linear (for example, exponential), the maximum rate of change from 200 to 500 mv is the most critical as this range may falsely trigger the esd circuitry. 2. over full recommended operating temperature range (see ta bl e 3 ). table 8. mpc8569e power dissipation power mode core frequency (mhz) platform frequency (mhz) ddr data rate frequency (mhz) quicc engine block frequency (mhz) v dd core (v) junction temperature ( c) power 5 notes typical 800 400 600 400 1.0 65 3.4 w 1, 2 thermal 105 4.9 w 1, 3 maximum 5.4 w 1, 4 typical 1067 533 667 533 1.0 65 3.9 w 1, 2 thermal 105 5.4 w 1, 3 maximum 6.0 w 1, 4
input clocks mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 43 2.3 input clocks the following table provides the syst em clock (sysclk) dc specifications. typical 1333 533 800 667 1.1 65 5.7 w 1, 2 thermal 105 7.9 w 1, 3 maximum 8.6 w 1, 4 note: 1. these values do not include power dissipation for i/o supplies. 2. typical power is an average value measured while running the dhrystone benchmark, using the nominal process and recommended core voltage (v dd ) at 65 c junction temperature (see ta b l e 3 ). 3. thermal power is the maximum power measured while running the dhrystone benchmark, using the worst case process and recommended core voltage (v dd ) at maximum operating junction temperature (see ta b l e 3 ). 4. maximum power is the maximum power measured while running a test which includes an entirely l1-cache-resident, contrived sequence of instructions that keeps the execution unit maximally busy and a typical workload on platform interfaces, using the worst case process and nominal core voltage (v dd ) at maximum operating junction temperature (see ta bl e 3 ). 5. this table includes power numbers for the v dd , av dd _ n , and scorevdd rails. table 9. sysclk dc electrical characteristics at recommended operating conditions with ov dd = 3.3 v 165 mv parameter symbol min typical max unit notes input high voltage v ih 2.0 ? ? v 1 input low voltage v il ??0 . 8v1 input capacitance c in ? 10.5 11.5 pf ? input current (v in = 0 v or v in = v dd) i in ?? 5 0 a2 note: 1. the min v il and max v ih values are based on the respective min and max ov in values found in ta bl e 3 . 2. the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 3 . table 8. mpc8569e power dissipation (continued) power mode core frequency (mhz) platform frequency (mhz) ddr data rate frequency (mhz) quicc engine block frequency (mhz) v dd core (v) junction temperature ( c) power 5 notes
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 input clocks freescale semiconductor 44 the following table provides the system clock (sysclk) ac timing specifications. 2.3.1 spread spectrum sources spread spectrum clock sources are an in creasingly popular way to control electro magnetic interference emissions (emi) by spreading the emitted noi se to a wider spectrum and reducing the peak no ise magnitude in order to meet industry and government requirements. these clock sources intentionally add long-term jitter to diffuse the emi spectral content. the jitter specification given in below table considers short-term (cycle-t o-cycle) jitter only. the clock generator?s cycle-to-cycle outp ut jitter should meet the mpc8569e input cycle-to-cycle jitter requirement. frequency modulation and spread are separate concerns; the mpc8569e is compatible with spread spectrum so urces if the recommendations lis ted in the following table are observed. caution the processor?s minimum and maximum sysclk and core frequencies must not be exceeded regardless of the type of clock source. therefore, systems in which the processor is operated at its maximum rated e500 core frequency should avoid violating the stated limits by using down-spreading only. table 10. sysclk ac timing specifications at recommended operating conditions with ov dd = 3.3 v 165 mv parameter/condition symbol min typ max unit notes sysclk frequency f sysclk 66 ? 133 mhz 1, 2 sysclk cycle time t sysclk 7.5 ? 15.15 ns 1, 2 sysclk duty cycle t khk / t sysclk/ddrclk 40 ? 60 % 2 sysclk slew rate ? 1 ? 4 v/ns 3 sysclk peak period jitter ? ? ? 150 ps ? sysclk jitter phase noise at ?56 dbc ? ? ? 500 khz 4 ac input swing limits at 3.3 v ov dd v ac 1.9 ? ? v ? notes: 1. caution: the relevant clock ratio settings must be chosen such that the resulting sysclk frequency do not exceed their respective maximum or minimum operating frequencies. 2. measured at the rising edge and/or the falling edge at ov dd /2. 3. slew rate as measured from 0.3 v ac at the center of peak to peak voltage at clock input. 4. phase noise is calculated as fft of tie jitter. table 11. spread spectrum clock source recommendations at recommended operating conditions with ov dd = 3.3 v 165 mv. parameter min max unit notes frequency modulation ? 60 khz ? frequency spread ? 1.0 % 1, 2 notes: 1. sysclk frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and maximum specifications given in ta b l e 1 0 . 2. maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of the device.
ddr2 and ddr3 sdram controller mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 45 2.3.2 real time clock timing the real time clock timing (rtc) input is sampled by the core complex bus cl ock (ccb_clk). the output of the sampling latch is then used as an input to the counters of the pic and the time base unit of the e500; there is no need for jitter specificati on. the minimum pulse width of the rtc signal must be greater than 2x the period of the ccb_clk. that is, minimum clock high time is 2 t ccb_clk , and minimum clock low time is 2 t ccb_clk . there is no minimum rtc frequency; rtc may be grounded if not needed. 2.3.3 gigabit ethernet reference clock timing the following table provides the gigabit ethernet reference clock (tx_clk) ac timing specifications. 2.3.4 other input clocks a description of the overall clocking of this device is available in the mpc8569e powerquicc iii integrated host processor family reference manual in the form of a clock subsystem block diagram. for information about the input clock requirements of other functional blocks such as serdes, ethe rnet management, esdhc, and enhanced local bus see the specific interface section. 2.4 ddr2 and ddr3 sdram controller this section describes the dc and ac electrical specificatio ns for the ddr2 and ddr3 sdram controller interface of the mpc8569e. note that the required gv dd (typ) is 1.8 v for ddr2 sdram and gv dd (typ) is 1.5 v for ddr3 sdram. table 12. tx_clk 3,4 ac timing specifications at recommended operating conditions with lv dd = 2.5 v 125 mv / 3.3 v 165 mv. parameter/condition symbol min typical max unit notes tx_clk frequency t g125 ?1 2 5?m h z? tx_clk cycle time t g125 ?8?n s? tx_clk rise and fall time lv dd = 2.5 v lv dd = 3.3 v t g125r /t g125f ?? 0.75 1.0 ns 1, 5 tx_clk duty cycle gmii, tbi 1000base-t for rgmii, rtbi t g125h /t g125 45 47 ? 55 53 %2, 5 tx_clk jitter ? ? ? 150 ps 2, 5 notes: 1. rise and fall times for tx_clk are measured from 0.5 and 2.0 v for lv dd = 2.5 v, and from 0.6 and 2.7 v for lv dd =3.3v. 2. tx_clk is used to generate the gtx clock for the uec transmitter with 2% degradation. the tx_clk duty cycle can be loosened from 47%/53% as long as the phy device can tolerate the duty cycle generated by the uec gtx_clk. see section 2.6.3.7, ?rgmii and rtbi ac timing specifications,? for duty cycle for 10base-t and 100base-t reference clock. 3. gigabit transmit 125-mhz source. this signal must be generat ed externally with a crystal or oscillator, or is sometimes provided by the phy. tx_clk is a 125-mhz input into the ucc ethernet controller and is used to generate all 125-mhz related signals and clocks in the following modes: gmii, tbi, rtbi, rgmii. 4. for gmii and tbi modes, tx_clk is provided to ucc1 through qe_pc[8:11,14,15] (clk9-12 ,15,16) and to ucc2 through qe_pc[2,3,6,7,15:17](clk3,4, 7,8,16:18). for rgmii and rtbi modes, tx_c lk is provided to ucc1 and ucc3 through qe_pc11(clk12) and to ucc2 and ucc4 through qe_pc16 (clk17). 5. system/board must be designed to ensure the input requirem ent to the device is achieved. proper device operation is guaranteed for inputs meeting this requirement by desi gn, simulation, characterization, or functional testing
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ddr2 and ddr3 sdram controller freescale semiconductor 46 2.4.1 ddr2 and ddr3 sdram interface dc electrical characteristics the following table provides the reco mmended operating conditions for the ddr sdram controller when interfacing to ddr2 sdram. the following table provides the reco mmended operating conditions for the ddr sdram controller when interfacing to ddr3 sdram. table 13. ddr2 sdram interface dc electrical characteristics at recommended operating condition with gv dd =1.8v 1 parameter symbol min max unit notes i/o reference voltage mvref n 0.49 gv dd 0.51 gv dd v2, 3, 4 input high voltage v ih mvref n +0.125 ? v 5 input low voltage v il ? mvref n ? 0.125 v 5 output high current (v out =1.320v) i oh ?? 1 3 . 4m a6 , 7 output low current (v out =0.380v) i ol 13.4 ? ma 6, 7 i/o leakage current i oz ?50 50 a8 notes: 1. gv dd is expected to be within 50 mv of th e dram?s voltage supply at all times. the dram?s and memory controller?s voltage supply may or may not be from the same source. 2. mvref n is expected to be equal to 0.5 gv dd and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mvref n may not exceed the mvref n dc level by more than 2% of gv dd (that is, 36 mv). 3. v tt is not applied directly to the device. it is the supply to wh ich far end signal termination is made, and it is expected to be equal to mvref n with a min value of mvref n ? 0.04 and a max value of mvref n +0.04. v tt should track variations in the dc level of mvref n . 4. the voltage regulator for mvref n must meet the specifications stated in ta bl e 1 6 . 5. input capacitance load for dq, dqs, and dqs are available in the ibis models. 6. i oh and i ol are measured at gv dd = 1.7 v. 7. refer to the ibis model for the complete output iv curve characteristics. 8. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 14. ddr3 sdram interface dc electrical characteristics at recommended operating condition with gv dd =1.5v 1 parameter symbol min max unit note i/o reference voltage mvref n 0.49 gv dd 0.51 gv dd v2, 3, 4
ddr2 and ddr3 sdram controller mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 47 the following table provides the ddr contro ller interface capacitance for ddr2 and ddr3. the following table provides the curr ent draw characteristics for mvref n. input high voltage v ih mvref n + 0.100 gv dd v5 input low voltage v il gnd mvref n ? 0.100 v 5 i/o leakage current i oz ?50 50 a6 notes: 1. gv dd is expected to be within 50 mv of th e dram?s voltage supply at all times. the dram?s and memory controller?s voltage supply may or may not be from the same source. 2. mvref n is expected to be equal to 0.5 gv dd and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mvref n may not exceed the mvref n dc level by more than 1% of gv dd (that is, 15 mv). 3. v tt is not applied directly to the device. it is the supply to wh ich far end signal termination is made, and it is expected to be equal to mvref n with a min value of mvref n ? 0.04 and a max value of mvref n +0.04. v tt should track variations in the dc level of mvref n . 4. the voltage regulator for mvref n must meet the specifications stated in ta bl e 1 6 . 5. input capacitance load for dq, dqs, and dqs are available in the ibis models. 6. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 15. ddr2 and ddr3 sdram capacitance at recommended operating conditions with gv dd of 1.8 v 5% for ddr2 or 1.5 v 5% for ddr3 parameter symbol min max unit notes input/output capacitan ce: dq, dqs, dqs c io 6 8 pf 1, 2 delta input/output ca pacitance: dq, dqs, dqs c dio ? 0.5 pf 1, 2 note: 1. this parameter is sampled. gvdd = 1.8 v 0.1 v (for ddr2), f = 1 mhz, t a =25c, v out = gvdd/2, v out (peak-to-peak) = 0.2 v. 2. this parameter is sampled. gvdd = 1.5 v 0.075 v (for ddr3), f = 1 mhz, t a =25c, v out = gvdd/2, v out (peak-to-peak) = 0.175 v. table 16. current draw characteristics for mvrefn for recommended operating conditions, see ta b l e 3 . parameter symbol min max unit notes current draw for ddr2 sdram for mvref n i mvref n ? 300 a? current draw for ddr3 sdram for mvref n i mvref n ? 250 a? table 14. ddr3 sdram interface dc electrical characteristics (continued) at recommended operating condition with gv dd =1.5v 1 parameter symbol min max unit note
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ddr2 and ddr3 sdram controller freescale semiconductor 48 2.4.2 ddr2 and ddr3 sdram interf ace ac timing specifications this section provides the ac timing specifications for the ddr sdram controller interface. the ddr controller supports both ddr2 and ddr3 memories. note that the required gv dd (typ) voltage is 1.8 v or 1.5 v when interfacing to ddr2 or ddr3 sdram respectively. 2.4.2.1 ddr2 and ddr3 sdram interface input ac timing specifications the following table provides th e input ac timing specifi cations for the ddr controller wh en interfacing to ddr2 sdram. the following table provides th e input ac timing specifi cations for the ddr controller wh en interfacing to ddr3 sdram. the following table provides the input ac timing specifications for the ddr controller when interfacing to ddr2 and ddr3 sdram. table 17. ddr2 sdram interface input ac timing specifications at recommended operating conditions with gv dd of 1.8 v 5% parameter symbol min max unit notes ac input low voltage > 533 mhz data rate v ilac ?m v r e f n ? 0.20 v ? 533 mhz data rate ? mvref n ? 0.25 ac input high voltage > 533 mhz data rate v ihac mvref n + 0.20 ? v ? 533 mhz data rate mvref n + 0.25 ? table 18. ddr3 sdram interface input ac timing specifications at recommended operating conditions with gv dd of 1.5 v 5% parameter symbol min max unit notes ac input low voltage v ilac ? mvref n ? 0.175 v ? ac input high voltage v ihac mvref n + 0.175 ? v ? table 19. ddr2 and ddr3 sdram interf ace input ac timi ng specifications 3 at recommended operating conditions with gv dd of 1.8 v 5% for ddr2 or 1.5 v 5% for ddr3 parameter symbol min max unit note controller skew for mdqs?mdq/mecc t ciskew ??p s1 800 mhz data rate ?200 200 1 667 mhz data rate ?240 240 1 533 mhz data rate ?300 300 1 400 mhz data rate ?365 365 1
ddr2 and ddr3 sdram controller mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 49 the following figure shows the ddr2 and ddr3 sdram interface input timing diagram. figure 8. ddr2 and ddr3 sdram interface input timing diagram tolerated skew for mdqs?mdq/mecc t diskew ??p s2 800 mhz data rate ?425 425 2 667 mhz data rate ?510 510 2 533 mhz data rate ?635 635 2 400 mhz data rate ?885 885 2 note: 1. t ciskew represents the total amount of skew consumed by the controller between mdqs[n] and any corresponding bit that is captured with mdqs[n]. this must be subt racted from the total timing budget. 2. the amount of skew that can be tolerated from mdqs to a corresponding mdq signal is called t diskew .this can be determined by the following equation: t diskew =(t 4 ? abs(t ciskew )) where t is the clock period and abs(t ciskew ) is the absolute value of t ciskew . 3. parameters tested in ddr2 mode are to 400, 533, 667, and 800 mhz data rates and in ddr3 mode to 667 and 800 mhz data rates. table 19. ddr2 and ddr3 sdram interf ace input ac timing specifications 3 (continued) at recommended operating conditions with gv dd of 1.8 v 5% for ddr2 or 1.5 v 5% for ddr3 parameter symbol min max unit note mck [ n ] mck[ n ] t mck mdq[x] mdqs[ n ] t diskew d1 d0 t diskew t diskew
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ddr2 and ddr3 sdram controller freescale semiconductor 50 2.4.2.2 ddr2 and ddr3 s dram interface output ac timing specifications the following table contains the output ac ti ming targets for the ddr2 and ddr3 sdram interface. table 20. ddr2 and ddr3 sdram interf ace output ac timing specifications 6 at recommended operating conditions with gv dd of 1.8 v 5% for ddr2 or 1.5 v 5% for ddr3. parameter symbol 1 min max unit notes mck[ n ] cycle time t mck 2.5 5 ns 2 addr/cmd output setup with respect to mck t ddkhas ns 3 800 mhz 667 mhz 533 mhz 400 mhz 0.917 7 0.88 8 1.10 1.48 1.95 ? ? ? ? addr/cmd output hold with respect to mck t ddkhax ns 3 800 mhz 667 mhz 533 mhz 400 mhz 0.917 7 0.88 8 1.10 1.48 1.95 ? ? ? ? mcs [ n ] output setup with respect to mck t ddkhcs ns 3 800 mhz 667 mhz 533 mhz 400 mhz 0.917 1.10 1.48 1.95 ? ? ? ? mcs [ n ] output hold with respect to mck t ddkhcx ns 3 800 mhz 667 mhz 533 mhz 400 mhz 0.917 1.10 1.48 1.95 ? ? ? ? mck to mdqs skew t ddkhmh ns 4 800 mhz 667 mhz ?0.375 ?0.6 0.375 0.6
ddr2 and ddr3 sdram controller mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 51 note for the addr/cmd setup and hold specifications in table 20 , it is assumed that the clock control register is set to adjust the memory clocks by ? applied cycle. mdq/mecc/mdm output setup with respect to mdqs t ddkhds, t ddklds ps 5 800 mhz 667 mhz 533 mhz 400 mhz 280 7 320 8 400 7 450 8 538 700 ? ? ? ? mdq/mecc/mdm output hold with respect to mdqs 800 mhz 667 mhz 533 mhz 400 mhz t ddkhdx, t ddkldx 280 7 320 8 400 7 450 8 538 700 ? ? ? ? ps 5 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the reference clock (kh or kl) until the output went invalid (ax or dx). for example, t ddkhas symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) ar e invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from t he crossing of the two signals 0.1 v. 3. addr/cmd includes all ddr sdram output signals except mck/mck , mcs , and mdq/mecc/mdm/mdqs. 4. note that t ddkhmh follows the symbol conventions described in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck[n] clock (k h) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the mdqs override bits (called wr_data_delay) in the ti ming_cfg_2 register. this will typically be set to the same delay as in ddr_sdram_clk_cntl[clk_adjust]. the timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. see the mpc8569e powerquicc iii integrated host processor family reference manual for a description and understanding of the timing modifications enabled by use of these bits. 5. determined by maximum possible skew between a data st robe (mdqs) and any corresponding bit of data (mdq), ecc (mecc), or data mask (mdm). the data strobe must be centered inside of the data eye at the pins of the microprocessor. 6. parameters tested in ddr2 mode are to 400, 533, 667, and 800 mhz data rate and in ddr3 mode to 667 and 800 mhz data rate. 7. ddr3 only 8. ddr2 only table 20. ddr2 and ddr3 sdram interf ace output ac timing specifications 6 at recommended operating conditions with gv dd of 1.8 v 5% for ddr2 or 1.5 v 5% for ddr3. parameter symbol 1 min max unit notes
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ddr2 and ddr3 sdram controller freescale semiconductor 52 the following figure shows the ddr2 and ddr3 sdram interf ace output timing for the mck to mdqs skew measurement (t ddkhmh ). figure 9. timing diagram for t ddkhmh the following figure shows the ddr2 and ddr3 sdram output timing diagram. figure 10. ddr2 and ddr3 output timing diagram t ddkhmhmax) = 0.6 ns or 0.375 ns mdqs mck [ n ] mck[ n ] t mck t ddkhmh(min) = ?0.6 ns or ?0.375 ns mdqs addr/cmd t ddkhas , t ddkhcs t ddklds t ddkhds mdq[x] mdqs[n] mck mck t mck t ddkldx t ddkhdx d1 d0 t ddkhax , t ddkhcx write a0 noop t ddkhme t ddkhmh t ddkhmp
duart mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 53 the following figure provides the ac test load for the ddr2 and ddr3 controller bus. figure 11. ddr2 and ddr3 controller bus ac test load 2.5 duart this section describes the dc and ac electrical specifications for the duart interface of the mpc8569e. 2.5.1 duart dc electrical characteristics the following table provides the dc electri cal characteristics for the duart interface. 2.5.2 duart ac electrical specifications the following table provides the ac tim ing parameters for the duart interface. table 21. duart dc electrical characteristics for recommended operating conditions, see ta b l e 3 parameter symbol min max unit notes input high voltage v ih 2?v1 input low voltage v il ?0 . 8v 1 input current (ov in = 0 v or ov in = ov dd )i in ?40 a2 output high voltage (ov dd = mn, i oh = ?2 ma) v oh 2.4 ? v ? output low voltage (ov dd = min, i ol = 2 ma) v ol ?0 . 4v? note: 1. the min v il and max v ih values are based on the min and max ov in respective values found in ta bl e 3 . 2. the symbol ov in represents the input voltage of th e supply. it is referenced in ta b l e 3 . table 22. duart ac timing specifications for recommended operating conditions, see ta bl e 3 parameter value unit notes minimum baud rate f ccb /1,048,576 baud 1 maximum baud rate f ccb /16 baud 1, 2 oversample rate 16 ? 3 notes: 1. f ccb refers to the internal platform clock. 2. the actual attainable baud rate is limited by the latency of interrupt processing. 3. the middle of a start bi t is detected as the 8 th sampled 0 after the 1-to-0 transition of the start bit. subsequent bit values are sampled each 16 th sample. output z 0 = 50 gv dd /2 r l = 50
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ethernet interface freescale semiconductor 54 2.6 ethernet interface this section provides the ac and dc el ectrical characteristics for the ethernet interfaces inside the quicc engine block. 2.6.1 gmii/sgmii/mii/smii/rmi i/tbi/rgmii/rtbi electrical characteristics the electrical characteristics specified he re apply to all gigabit media independent interface (gmii), serial gigabit media independent interface (sgmii), media indepe ndent interface (mii), ten-bit interface (t bi), reduced gigabit media independent interface (rgmii), reduced ten-bit interface (rtbi), and reduced media independent interface (rmii) signals except management data input/output (mdio) and management data clock (mdc). the rgmii and rtbi interfaces are defined for 2.5 v, while the gmii and tbi interfaces are defined for 3.3 v. the gmii, mii, and tbi interf ace timing is compatible with ieee std 802.3?. the rgmii and rtbi interfaces follow the reduced gigabit media-independent interface (rgmii) specification version 1.3 (12/10/2000) . the rmii interface follows the rmii consortium rmii specification version 1.2 (3/20/1998) . the electrical characteristics for the sgmii is specified in section 2.6.4, ?sgmii interface electrical characteristics.? the electrical characteristics for mdio and mdc are specified in section 2.7, ?ethernet management interface.? 2.6.2 gmii, mii, rmii, smii, tbi, rg mii and rtbi dc electrical characteristics the following table shows the gmii, mii, rmii, smii, and tbi dc electrical characteristics when operating from a 3.3 v supply. the following table shows the rgmii, and rtbi dc electrical characteristics when operating from a 2.5 v supply. table 23. gmii, mii, rmii, smii, and tbi dc electrical characteristics at recommended operating conditions with lv dd =3.3v parameter symbol min max unit notes input high voltage v ih 2.0 ? v 1 input low voltage v il ?0 . 9 0v? input high current (v in = lv dd )i ih ?4 0 a2 input low current (v in = gnd) i il ?600 ? a2 output high voltage (lv dd = min, i oh = ?4.0 ma) v oh 2.1 lv dd + 0.3 v ? output low voltage (lv dd = min, i ol = 4.0 ma) v ol gnd 0.50 v ? note: 1. the min v il and max v ih values are based on the respective min and max lv in values found in ta b l e 3 . 2. the symbol v in , in this case, represents the lv in symbols referenced in ta b l e 2 and ta b l e 3 . table 24. rgmii and rtbi dc electrical characteristics at recommended operating conditions with lv dd =2.5v parameter symbol min max unit note input high voltage v ih 1.70 ? v ? input low voltage v il ?0 . 7 0v? input high current (v in = lv dd )i ih ?1 0 a1
ethernet interface mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 55 2.6.3 gmii, mii, rmii, smii, tbi, rgmii, and rtbi ac timing specifications this section describes the ac timing specifications for gmii, mii, rmii, smii, tbi, rgmii, and rtbi. 2.6.3.1 gmii timing specifications this section describe the gmii transm it and receive ac timing specifications. 2.6.3.1.1 gmii transmit ac timing specifications the following table provides the gmii transmit ac timing specifications. the following figure shows the gmii transmit ac timing diagram. figure 12. gmii transmit ac timing diagram input low current (v in = gnd) i il ?15 ? a1, 2 output high voltage (lv dd = min, i oh = ?1.0 ma) v oh 2.00 lv dd + 0.3 v ? output low voltage (lv dd =min, i ol = 1.0 ma) v ol gnd ? 0.3 0.40 v ? note: 1. the symbol v in , in this case, represents the lv in symbols referenced in ta b l e 2 and ta b l e 3 . 2. the min v il and max v ih values are based on the respective min and max lv in values found in ta b l e 3 . table 25. gmii transmit ac timing specifications for recommended operating conditions, see ta bl e 3 parameter symbol min typ max unit note gtx_clk clock period t gtx 7.5 ? 8.5 ns ? gmii data txd[7:0], tx_er, tx_en setup time t gtkhdv 2.5??ns? gtx_clk to gmii data txd[7: 0], tx_er, tx_en delay t gtkhdx 0.5??ns? gtx_clk data clock rise time (20%?80%) t gtxr ?1.0?ns? gtx_clk data clock fall time (80%?20%) t gtxf ?1.0?ns? table 24. rgmii and rtbi dc electrical characteristics (continued) at recommended operating conditions with lv dd =2.5v parameter symbol min max unit note gtx_clk txd[7:0] t gtkhdx t gtx t gtxh t gtxr t gtxf t gtkhdv tx_en tx_er
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ethernet interface freescale semiconductor 56 2.6.3.1.2 gmii receive ac timing specifications the following table provides the gm ii receive ac timing specifications. the following figure provides the gmii ac test load. figure 13. gmii ac test load the following figure shows the gmii receive ac timing diagram. figure 14. gmii receive ac timing diagram 2.6.3.2 mii ac timing specifications this section describes the mii transmit and receive ac tim ing specifications. table 26. gmii receive ac timing specifications for recommended operating conditions, see ta b l e 3 parameter symbol min typ max unit note rx_clk clock period t grx 7.5 ? ? ns 1 rx_clk duty cycle t grxh /t grx 35 ? 65 % 2 rxd[7:0], rx_dv, rx_er setup time to rx_clk t grdvkh 2.0 ? ? ns ? rxd[7:0], rx_dv, rx_er hold time to rx_clk t grdxkh 0.2 ? ? ns ? rx_clk clock rise time (20%?80%) t grxr ??1.0 ns2 rx_clk clock fall time (80%?20%) t grxf ??1.0 ns2 note: 1. the frequency of rx_clk should not exceed frequency of gigabit ethernet reference clock by more than 300 ppm 2. system/board must be designed to ensure the input requirement to the device is achieved. proper device operation is guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing output z 0 = 50 lv dd /2 r l = 50 rx_clk rxd[7:0] t grdxkh t grx t grxh t grxr t grxf t grdvkh rx_dv rx_er
ethernet interface mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 57 2.6.3.2.1 mii transmit ac timing specifications the following table provides the mi i transmit ac timing specifications. the following figure shows the mii transmit ac timing diagram. figure 15. mii transmit ac timing diagram 2.6.3.2.2 mii receive ac timing specifications the following table provides the mi i receive ac timing specifications. table 27. mii transmit ac timing specifications for recommended operating conditions, see ta bl e 3 parameter symbol min typ max unit note tx_clk clock period 10 mbps t mtx 399.96 400 400.04 ns ? tx_clk clock period 100 mbps t mtx 39.996 40 40.004 ns ? tx_clk duty cycle t mtxh/ t mtx 35 ? 65 % ? tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx 0 ? 25 ns ? tx_clk data clock rise (20%?80%) t mtxr 1.0 ? 4.0 ns ? tx_clk data clock fall (80%?20%) t mtxf 1.0 ? 4.0 ns ? table 28. mii receive ac timing specifications for recommended operating conditions, see ta bl e 3 parameter symbol min typ max unit note rx_clk clock period 10 mbps t mrx 399.96 400 400.04 ns 1 rx_clk clock period 100 mbps t mrx 39.996 40 40.004 ns 1 rx_clk duty cycle t mrxh /t mrx 35 ? 65 % 2 rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10.0 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10.0 ? ? ns rx_clk clock rise (20%?80%) t mrxr 1.0 ? 4.0 ns 2 rx_clk clock fall time (80%?20%) t mrxf 1.0 ? 4.0 ns 2 note: 1. the frequency of rx_clk should not exceed the frequency of tx_clk by more than 300 ppm. 2. system/board must be designed to ensure the input requirement to the device is achieved. proper device operation is guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing. tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ethernet interface freescale semiconductor 58 the following figure provides the mii ac test load. figure 16. mii ac test load the following figure shows the mii receive ac timing diagram. figure 17. mii receive ac timing diagram 2.6.3.3 smii ac timing specification the following table shows the smii timing specifications. the following figure shows the smii mode signal timing. figure 18. smii mode signal timing table 29. smii mode signal timing for recommended operating conditions, see ta b l e 3 parameter symbol min max unit note ethsync_in, ethrxd to ethclock rising edge setup time t smdvkh 1.5 ? ns ? ethclock rising edge to ethsync_in, ethrxd hold time t smdxkh 1.0 ? ns ? ethclock rising edge to ethsync, ethtxd output delay t smxr 1.5 5.5 ns ? output z 0 = 50 lv dd /2 r l = 50 rx_clk rxd[3:0] t mrdxkl t mrx t mrxh t mrxr t mrxf rx_dv rx_er t mrdvkh valid data valid ethclock ethsync_in ethrxd ethsync ethtxd valid valid t smxr t smdxkh t smdvkh
ethernet interface mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 59 2.6.3.4 rmii ac timing specifications this section describes the rmii trans mit and receive ac timing specifications. 2.6.3.4.1 rmii transmit ac timing specifications the following table shows the rmii transmit ac timing specifications. the following figure shows the rmii transmit ac timing diagram. figure 19. rmii transmit ac timing diagram 2.6.3.4.2 rmii receive ac timing specifications the following table provides the rm ii receive ac timing specifications. table 30. rmii transmit ac timing specifications for recommended operating conditions, see ta bl e 3 parameter symbol min typ max unit note ref_clk clock period t rmt ? 20.0 ? ns ? ref_clk duty cycle t rmth 35 ? 65 % ? ref_clk peak-to-peak jitter t rmtj ??250ps? rise time ref_clk (20%?80%) t rmtr 1.0 ? 4.0 ns ? fall time ref_clk (80%?20%) t rmtf 1.0 ? 4.0 ns ? ref_clk to rmii data txd[1:0], tx_en delay t rmtdx 2.0 ? 10.0 ns ? table 31. rmii receive ac timing specifications for recommended operating conditions, see ta bl e 3 parameter symbol min typ max unit note ref_clk clock period t rmr ? 20.0 ? ns ? ref_clk duty cycle t rmrh 35 ? 65 % 1 ref_clk peak-to-peak jitter t rmrj ? ? 250 ps 1 rise time ref_clk (20%?80%) t rmrr 1.0 ? 4.0 ns 1 ref_clk txd[1:0] t rmtdx t rmt t rmth t rmtr t rmtf tx_en tx_er
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ethernet interface freescale semiconductor 60 the following figure provides the ac test load. figure 20. ac test load the following figure shows the rmii receive ac timing diagram. figure 21. rmii receive ac timing diagram 2.6.3.5 tbi ac timing specifications this section describes the tbi transmit and receive ac timing specifications. fall time ref_clk (80%?20%) t rmrf 1.0 ? 4.0 ns 1 rxd[1:0], crs_dv, rx_er set up time to ref_clk rising edge t rmrdv 4.0 ? ? ns ? rxd[1:0], crs_dv, rx_er hold time to ref_clk rising edge t rmrdx 2.0 ? ? ns ? note: 1. system/board must be designed to ensure the input requirement to the device is achieved. proper device operation is guaranteed for inputs meeting this requirement by desi gn, simulation, characterization, or functional testing. table 31. rmii receive ac timing specifications (continued) for recommended operating conditions, see ta bl e 3 parameter symbol min typ max unit note output z 0 = 50 lv dd /2 r l = 50 ref_clk rxd[1:0] t rmrkhdx t rmr t rmrh t rmrr t rmrf crs_dv rx_er t rmrdvkh valid data
ethernet interface mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 61 2.6.3.5.1 tbi transmit ac timing specifications the following table provides the tb i transmit ac timing specifications. the following figure shows the tbi transmit ac timing diagram. figure 22. tbi transmit ac timing diagram 2.6.3.5.2 tbi receive ac timing specifications the following table provides the tbi receive ac timing specifications. table 32. tbi transmit ac timing specifications for recommended operating conditions, see ta bl e 3 parameter symbol min typ max unit note gtx_clk clock period t gtx ?8.0?ns? tcg[9:0] setup time gtx_clk going high t ttkhdv 2.0 ? ? ns ? gtx_clk to tcg[9:0] delay time t ttkhdx 1.0 ? ? ns 1 gtx_clk rise (20%?80%) t ttxz 0.7 ? ? ns ? gtx_clk fall time (80%?20%) t ttxf 0.7 ? ? ns ? note: 1. data valid t ttkhdv to gtx_clk minimum setup time is a function of clock and maximum hold time (min setup = cycle time ? max delay). table 33. tbi receive ac timing specifications for recommended operating conditions, see ta bl e 3 parameter symbol min typ max unit note pma_rx_clk[0:1] clock period t trx ? 16.0 ? ns 1 pma_rx_clk[0:1] skew t sktrx 7.5 ? 8.5 ns ? pma_rx_clk[0:1] duty cycle t trxh /t trx 40 ? 60 % 2 rcg[9:0] setup time to rising pma_rx_clk t trdvkh 2.5 ? ? ns ? gtx_clk tcg[9:0] t ttx t ttxh t ttxr t ttxf t ttkhdv t ttkhdx
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ethernet interface freescale semiconductor 62 the following figure provides the ac test load. figure 23. ac test load the following figure shows the tbi receive ac timing diagram. figure 24. tbi receive ac timing diagram rcg[9:0] hold time to rising pma_rx_clk t trdxkh 1.5 ? ? ns ? pma_rx_clk[0:1] clock rise time (20%?80%) t trxr 0.7 ? 2.4 ns 2 pma_rx_clk[0:1] clock fall time (80%?20%) t trxf 0.7 ? 2.4 ns 2 note: 1. the frequency of rx_clk should not exceed the frequency of gigabit ethernet reference clock by more than 300 ppm. 2. system/board must be designed to ensu re the input requirement to the device is achieved. proper device operation is guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing. table 33. tbi receive ac timing specifications (continued) for recommended operating conditions, see ta bl e 3 parameter symbol min typ max unit note output z 0 = 50 lv dd /2 r l = 50 pma_rx_clk1 rcg[9:0] t trx t trxh t trxr t trxf t trdvkh pma_rx_clk0 t trdxkh t trdvkh t trdxkh t sktrx t trxh valid data valid data
ethernet interface mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 63 2.6.3.6 tbi single-clock mode ac specifications the following table shows the tbi single-cl ock mode receive ac timing specifications. the following figure shows the tbi single -clock mode receive ac timing diagram. figure 25. tbi single-clock mode receive ac timing diagram 2.6.3.7 rgmii and rtbi ac timing specifications the following table presents the rgmi i and rtbi ac timing specifications. table 34. tbi single-clock mode r eceive ac timing specifications for recommended operating conditions, see ta bl e 3 parameter symbol min typ max unit note rx_clk clock period t trr 7.5 8.0 8.5 ns 1 rx_clk duty cycle t trrh 40 50 60 % 2 rx_clk peak-to-peak jitter t trrj ??250ps 2 rise time rx_clk (20%?80%) t trrr ??? ns 2 fall time rx_clk (80%?20%) t trrf ??? ns 2 rcg[9:0] setup time to rx_clk rising edge t trrdv 2.0 ? ? ns ? rcg[9:0] hold time to rx_clk rising edge t trrdx 1.0 ? ? ns ? note: 1. the frequency of rx_clk should not exceed the frequency of gigabit ethernet reference clock by more than 300 ppm. 2. system/board must be designed to ens ure the input requirement to the device is achieved. proper device operation is guaranteed for inputs meeting this requirement by design , simulation, characterization, or functional testing. table 35. rgmii and rtbi ac timing specifications for recommended operating conditions, see ta bl e 3 parameter symbol 1 min typ max unit notes data to clock output skew (at transmitter) t skrgt_tx ?500 0 500 ps 5 data to clock input skew (at receiver) t skrgt_rx 1.2 ? 2.6 ns 2 clock period duration t rgt 7.2 8.0 8.8 ns 3 duty cycle for 10base-t and 100base-tx t rgth /t rgt 40 50 60 % 3, 4, 6 t trr t trrh t trrf t trrr rx_clk rcg[9:0] valid data t trrdx t trrdv
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ethernet interface freescale semiconductor 64 duty cycle for gigabit t rgth /t rgt 45 50 55 % 6 rise time (20%?80%) t rgtr ? ? 1.75 ns 6 fall time (20%?80%) t rgtf ? ? 1.75 ns 6 notes: 1. in general, the clock reference symbol representation for this section is based on the symbols rgt to represent rgmii and rtbi timing. for example, the subscript of t rgt represents the tbi (t) receive (rx) cloc k. note also that the notation for rise (r) and fall (f) times follows the clock symbol that is being represented. for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (rgt). 2. this implies that pc board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. many phy vendors alread y incorporate the necessary dela y inside their chip. if so, additional pcb delay is probably not needed. 3. for 10 and 100 mbps, t rgt scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t rgt of the lowest speed transitioned between. 5. the frequency of rx_clk should not exceed the frequency of gigabit ethernet reference clock by more than 300 ppm. 6. system/board must be designed to ensure the input requirement to the device is achieved. proper device operation is guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing. table 35. rgmii and rtbi ac timi ng specifications (continued) for recommended operating conditions, see ta bl e 3 parameter symbol 1 min typ max unit notes
ethernet interface mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 65 the following figure shows the rgmii and rtbi ac timing and multiplexing diagrams. figure 26. rgmii and rtbi ac timing and multiplexing diagrams 2.6.4 sgmii interface elec trical characteristics each sgmii port features a 4-wire ac -coupled serial link from the serdes interface of mpc8569e as shown in figure 27 , where c tx is the external (on board) ac-coupled capacitor. each output pin of the serdes transmitter differential pair features 50- output impedance. each input of the serd es receiver differential pair features 50- on-die termination to gnd. the reference circuit of the serdes transmitter and receiver is shown in figure 45 . 2.6.4.1 sgmii dc electrical characteristics this section discusses the electrical characteristics for the sgmii interface. 2.6.4.1.1 dc requirements for sgmii sd_ref_clk and sd_ref_clk the characteristics and dc requirements of the se parate serdes reference clock are described in section 2.9.2.3, ?dc level requirement for serdes reference clocks.? gtx_clk t rgt t rgth t skrgt_tx tx_ctl txd[8:5] txd[7:4] txd[9] txerr txd[4] txen txd[3:0] (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_clk (at phy) rx_ctl rxd[8:5] rxd[7:4] rxd[9] rxerr rxd[4] rxdv rxd[3:0] rx_clk (at phy) t skrgt_rx t skrgt_rx t skrgt_tx t rgth t rgt gtx_clk (at receiver) rxd[8:5][3:0] rxd[7:4][3:0]
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ethernet interface freescale semiconductor 66 2.6.4.1.2 sgmii transmit dc timing specifications table 36 and table 37 describe the sgmii serdes transmitter and r eceiver ac-coupled dc el ectrical characteristics. transmitter dc characteristics are measur ed at the transmitter outputs, sd_tx[ n ] and sd_tx [ n ], as shown in figure 28 . table 36. sgmii dc transmitter electrical characteristics at recommended operating conditions with xv dd = 1.0 v 3% and 1.1 v 3%. parameter symbol min typ max unit notes output high voltage v oh ??x v dd-typ /2 + |v od | -max /2 mv 1 output low voltage v ol xv dd-typ /2 ? |v od | -max /2 ??mv1 output differential voltage 2, 3, 4 (xv dd-typ at 1.0 v) |v od | 320.0 500.0 725.0 mv equalization setting: 1.0 293.8 459.0 665.6 equalization setting: 1.09 266.9 417.0 604.7 equalization setting: 1.2 240.6 376.0 545.2 equalization setting: 1.33 213.1 333.0 482.9 equalization setting: 1.5 186.9 292.0 423.4 equalization setting: 1.71 160.0 250.0 362.5 equalization setting: 2.0
ethernet interface mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 67 output differential voltage 2, 3, 4 (xv dd-typ at 1.1 v) |v od | 352.0 550.0 797.5 mv equalization setting: 1.0 323.1 504.9 732.1 equalization setting: 1.09 293.6 458.7 665.1 equalization setting: 1.2 264.7 413.6 599.7 equalization setting: 1.33 234.4 366.3 531.1 equalization setting: 1.5 205.6 321.2 465.7 equalization setting: 1.71 176.0 275.0 398.8 equalization setting: 2.0 output impedance (single-ended) r o 40 50 60 ? notes: 1. this does l not align to dc-coupled sgmii. 2. |v od | = |v sd_txn ? v sd_tx n |. |v od | is also referred as output differential peak voltage. v tx-diffp-p = 2 |v od |. 3. the |v od | value shown in the table assumes the following transmit equalization setting in the xmiteq ab (for serdes lanes 0 & 1) or xmiteq ef (for serdes lanes 2 & 3) bit field of the mpc8569e serdes control register: ? the msb (bit 0) of the above bit field is set to zero (selecting the full v dd-diff-p-p amplitude?power up default); ? the lsb (bit [1:3]) of the above bit field is set based on the equalization setting shown in table. 4. the |v od | value shown in the typ column is based on the condition of xv dd-typ = 1.0v and 1.1 v, no common mode offset variation, serdes transmitter is terminated with 100- differential load between sd_tx[ n ] and sd_tx [ n ]. table 36. sgmii dc transmitter electrical characteristics (continued) at recommended operating conditions with xv dd = 1.0 v 3% and 1.1 v 3%. parameter symbol min typ max unit notes
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ethernet interface freescale semiconductor 68 the following figure shows an example of a 4-wire ac-coupled sgmii serial link connection. figure 27. 4-wire ac-coupled sgmii serial link connection example the following figure shows the sgmii transmitter dc measurement circuit. figure 28. sgmii transmitter dc measurement circuit mpc8569e sgmii serdes interface transmitter sd_txn sd_rxm sd_ tx n sd_ rx m receiver c tx c tx sd_rx n sd_ rx n receiver transmitter sd_ tx m c tx c tx 50 50 50 50 50 50 50 50 sd_txm 50 transmitter sd_tx n sd_tx n 50 v od mpc8569e sgmii serdes interface 50 50
ethernet interface mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 69 2.6.4.1.3 sgmii dc receive r electrical characteristics the following table lists the sgmii dc r eceiver electrical characteristi cs. source synchronous clocking is not supported. clock is recovered from the data. s 2.6.4.2 sgmii ac timing specifications this section discusses the ac timing specifications for the sgmii interface. 2.6.4.2.1 ac requirements for sgmii sd_ref_clk and sd_ref_clk note that the sgmii clock requirem ents for sd_ref_clk and sd_ref_clk are intended to be used within the clocking guidelines specified by section 2.9.2.4, ?ac requirements for serdes reference clocks.? table 37. sgmii dc receiver electrical characteristics at recommended operating conditions with xv dd = 1.0 v 3% and 1.1 v 3%. parameter symbol min typ max unit notes dc input voltage range ? n/a ? 1 input differential voltage lsts = 001 v rx_diffp-p 100 ? 1200 mv 2, 4 lsts = 100 175 ? loss of signal threshold lsts = 001 v los 30 ? 100 mv 3, 4 lsts = 100 65 ? 175 receiver differential input impedance z rx_diff 80 ? 120 ? notes: 1. input must be externally ac-coupled. 2. v rx_diffp-p is also referred to as peak-to-peak input differential voltage. 3. the concept of this parameter is equi valent to the electrical idle detect threshold parameter in pci express. see section 2.10.2, ?pci express dc physical layer specifications,? and section 2.10.3, ?pci express ac physical layer specifications ,? for further explanation. 4. the lsts shown in this table refers to the lsts 2 or lsts 3 bit field of the mpc8569e?s se rdes control register srdscr4.
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ethernet interface freescale semiconductor 70 2.6.4.2.2 sgmii transmit ac timing specifications the following table provides the sgmii transmit ac timing specifications. a source synchronous clock is not supported. the ac timing specifications do not include refclk jitter. 2.6.4.2.3 sgmii ac measurement details transmitter and receiver ac characteristics ar e measured at the tr ansmitter outputs (sd_tx n and sd_tx n ) or at the receiver inputs (sd_rx n and sd_rx n ), as depicted in the fo llowing figure, respectively. figure 29. sgmii ac test/measurement load 2.6.4.2.4 sgmii receiver ac timing specifications the following table provides the sgmii receive ac timing speci fications. the ac timing specifica tions do not include refclk jitter. source synchronous clocking is not sup ported. clock is recovered from the data. table 38. sgmii transmit ac timing specifications at recommended operating conditions with xv dd = 1.0 v 3% and 1.1 v 3%. parameter symbol min typ max unit notes deterministic jitter jd ? ? 0.17 ui p-p ? total jitter jt ? ? 0.35 ui p-p 2 unit interval ui 799.92 800 800.08 ps 1 ac coupling capacitor c tx 75 100 200 nf 3 notes: 1. each ui is 800 ps 100 ppm. 2. see figure 30 for single frequency si nusoidal jitter limits. 3. the external ac coupling capacitor is required. it is reco mmended that it be placed near the device transmitter outputs. table 39. sgmii receive ac timing specifications at recommended operating conditions with xv dd = 1.0 v 3%. and 1.1 v 3%. parameter symbol min typ max unit notes deterministic jitter tolerance jd 0.37 ? ? ui p-p 1, 2, 4 combined deterministic and random jitter tolerance jdr 0.55 ? ? ui p-p 1, 2, 4 tx silicon + package c = c tx c = c tx r = 50 r = 50 d+ package pin d? package pin d+ package pin
ethernet interface mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 71 the sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of the followin g figure. figure 30. single frequency sinusoidal jitter limits total jitter tolerance jt 0.65 ? ? ui p-p 1, 2, 4 bit error ratio ber ? ? 10 -12 ?? unit interval ui 799.92 800.00 800.08 ps 3 notes: 1. measured at receiver. 2. see rapidio 1x/4x lp serial physical layer specification for interpretation of jitter specifications. 3. each ui is 800 ps 100 ppm. 4. system/board must be designed to ensure the input requirement to the device is achieved. proper device operation is guar- anteed for inputs meeting this requirement by design, simulation, characterization, or functional testing. table 39. sgmii receive ac timing specifications (continued) at recommended operating conditions with xv dd = 1.0 v 3%. and 1.1 v 3%. parameter symbol min typ max unit notes 8.5 ui p-p 0.10 ui p-p sinusoidal jitter amplitude 22.1 khz 1.875 mhz 20 mhz frequency
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ethernet interface freescale semiconductor 72 2.6.5 quicc engine block ieee 1588 ac specifications the following table provides the quicc engi ne block ieee 1588 ac timing specifications. the following figure shows the data and command output ac timing diagram. 1 quicc engine block ieee 1588 output ac timing: the output delay is counted starting at the rising edge if t t11588clkout is non-inverting. otherwise, it is counted starting at the falling edge. figure 31. quicc engine block ieee 1588 out put ac timing table 40. quicc engine block i eee 1588 ac timing specifications parameter symbol min typ max unit notes qe_1588_clk clock period t t1588clk 3.8 ? t rx_clk 7 ns 1, 3 qe_1588_clk duty cycle t t1588clkh / t t1588clk 40 50 60 % 5 qe_1588_clk peak-to-peak jitter t t1588clkinj ??2 5 0p s5 rise time qe_1588_clk (20%?80%) t t1588clkinr 1.0 ? 2.0 ns 5 fall time qe_1588_clk (80%?20%) t t1588clkinf 1.0 ? 2.0 ns 5 qe_1588_clk_out clock period t t1588clkout 2t t1588clk ??ns? qe_1588_clk_out duty cycle t t1588clkoth / t t1588clkout 30 50 70 % ? qe_1588_pps_out t t1588ov 0.5 ? 4.0 ns ? qe_1588_trig_in pulse width t t1588trigh 2t t1588clk_ max ??ns2 qe_ptp_sof_tx_in pulse width t t1588trigh t tx_clk 2 ? ? ns 4 qe_ptp_sof_rx_in pulse width t t1588trigh t rx_clk 2 ? ? ns 4 notes: 1. t rx_clk is the max clock period of the quicc engine block?s receiving cloc k selected by tmr_ ctrl[cksel]. see the quicc engine block with protocol interworking reference manual, for a description of tmr_ctrl registers. 2. it needs to be at least two times the clock period of the clock selected by tmr_ctrl[cksel]. see the quicc engine block with protocol interworking reference manual, for a description of tmr_ctrl registers. 3. the maximum value of t t1588clk is not only defined by the value of t rx_clk , but also defined by the recovered clock. for example, for 10/100/1000 mbps modes, the maximum value of t t1588clk are 2800, 280, and 56 ns, respectively. 4. the minimum value of t tx/rxclk is defined by the recovered clock. for exampl e, for 10/100/1000 mbps modes, the value of t tx/rxclk are 800, 80, and 16 ns, respectively. 5. system/board must be designed to ensure the input requirement to the device is achieved. proper device operation is guaranteed for inputs meeting this requirement by desi gn, simulation, characterization, or functional testing. qe_1588_clk_out qe_1588_pps_out t t1588ov t t1588clkout t t1588clkouth
ethernet management interface mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 73 the following figure shows the data and command input ac timing diagram. figure 32. quicc engine bloc k ieee 1588 input ac timing the following figure shows the data and command input ac timing diagram. figure 33. quicc engine block ieee 1588 input ac timing (sof trig) 2.7 ethernet management interface the electrical characteristics specified in this section apply to the mii management interface signals management data input/output (mdio) and management data clock (mdc). the el ectrical characteristics for gmii , rgmii, tbi, and rtbi are specified in section 2.6, ?ethernet interface.? 2.7.1 mii management dc electrical characteristics the mdc and mdio are defined to operate at a supply volt age of 3.3 v. the following table provides the dc electrical characteristics for mdio and mdc. table 41. mii management dc electrical characteristics at recommended operating conditions with lv dd = 3.3 v parameter symbol min max unit notes input high voltage v ih 2.0 ? v ? input low voltage v il ?0.90 v ? input high current (lv dd = max, v in = 2.1 v) i ih ?4 0 a1 qe_1588_clk qe_1588_trig_in t t1588clk t t1588trigh t t1588clkh tx_clk/rx_clk qe_ptp_sof_tx_in/ t ttx/rxclk qe_ptp_sof_rx_in t t1588trigh t t1588clkh
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 ethernet management interface freescale semiconductor 74 2.7.1.1 mii management ac electrical specifications the following table provides the mii management ac timing specifications. input low current (lv dd = max, v in = 0.5 v) i il ?600 ? a1 output high voltage (lv dd = min, i oh = ?4.0 ma) v oh 2.4 ? v ? output low voltage (lv dd = min, i ol = 4.0 ma) v ol ?0.4 v ? note: 1. the symbol v in , in this case, represents the lv in symbol referenced in ta b l e 2 and ta bl e 3 . table 42. mii management ac timing specifications at recommended operating conditions with lv dd = 3.3 v 5%. parameter symbol 1 min typ max unit notes mdc frequency f mdc ?2 . 5?m h z2 mdc period t mdc ?4 0 0?n s? mdc clock pulse width high t mdch 32 ? ? ns ? mdc to mdio valid t mdkhdv 2 (t plb_clk *8) ? ? ns 4 mdc to mdio delay t mdkhdx (16 t plb_clk ) ? 3 ? (16 t plb_clk ) + 3 ns 3, 4, 5 mdio to mdc setup time t mddvkh 10 ? ? ns ? mdio to mdc hold time t mddxkh 0??n s? mdc rise time t mdcr ? ? 10 ns ? mdc fall time t mdcf ? ? 10 ns ? notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outputs (d) are invalid (x) or data hold time. also, t mddvkh symbolizes management data timing (md) with respect to the time data input signals (d) reaching the valid state (v) relative to the t mdc clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropri ate letter: r (rise) or f (fall). 2. this parameter is dependent on the platform clock frequency (miimcfg [mgmtclk] field determi nes the clock frequency of the mgmt clock ce_mdc). 3. this parameter is dependent on the platform clock frequency. the delay is equal to 16 platform clock periods 3 ns. for example, with a platform clock of 400 mhz, the min/max delay is 40 ns 3 ns. 4. t plb_clk is the quicc engine block clock/2. 5. mdc to mdio data valid t mdkhdv is a function of clock period and max delay time (t mdkhdx ). (min setup = cycle time ? max delay table 41. mii management dc electrical characteristics (continued) at recommended operating conditions with lv dd = 3.3 v parameter symbol min max unit notes
hdlc, bisync, transparent, an d synchronous uart interfaces mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 75 the following figure shows the mii management ac timing diagram. figure 34. mii management interface timing diagram 2.8 hdlc, bisync, transparent, and synchronous uart interfaces this section describes the dc and ac electrical specificat ions for the high level data link control (hdlc), bisync, transparent, and synchronous ua rt interfaces of the mpc8569e. 2.8.1 hdlc, bisync, transparent, an d synchronous uart dc electrical characteristics the following table provides the dc electrical characteristics for the hdlc, bisync, transparent, and synchronous uart interfaces. table 43. hdlc, bisync, and transparent dc electrical characteristics for recommended operating conditions, see ta bl e 3 parameter symbol min max unit notes input high voltage v ih 2?v 1 input low voltage v il ?0 . 8 v 1 input current (ov in = 0 v or ov in = ov dd )i in ? 4 0 a2 output high voltage (ov dd = min, i oh = ?2 ma) v oh 2.4 ? v ? output low voltage (ov dd = min, i ol = 2 ma) v ol ?0 . 4 v ? note: 1. the min v il and max v ih values are based on the respective min and max ov in values found in ta b l e 3 . 2. the symbol ov in represents the input voltage of th e supply. it is referenced in ta b l e 3 . mdc t mddxkh t mdc t mdch t mdcr t mdcf t mdkhdx mdio mdio (input) (output) t mddvkh
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 hdlc, bisync, transparent, an d synchronous uart interfaces freescale semiconductor 76 2.8.2 hdlc, bisync, transparent, and synchronous uart ac timing specifications the following table provides the input and output ac timing specifications for the hdlc, bisync, and transparent protocols. the following table provides the input and output ac timing specifications for the synchronous uart protocols. table 44. hdlc, bisync, and tran sparent ac timing specifications for recommended operating conditions, see ta bl e 3 characteristic symbol 1 min max unit notes outputs?internal clock delay t hikhov 05 . 5n s2 outputs?external clock delay t hekhov 18 . 4n s2 outputs?internal clock high impedance t hikhox 05 . 5n s2 outputs?external clock high impedance t hekhox 18n s2 inputs?internal clock input setup time t hiivkh 6?n s? inputs?external clock input setup time t heivkh 4?n s? inputs?internal clock input hold time t hiixkh 0?n s? inputs?external clock input hold time t heixkh 1.3 ? ns ? notes: 1. the symbols used for timing specifications follow the pattern t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t hikhox symbolizes the outputs internal timing (hi) for the time t serial memory clock reference (k) goes from the hi gh state (h) until outputs (o) are invalid (x). 2. output specifications are measured from the 50% level of the rising edge of clki n to the 50% level of the signal. timings are measured at the pin. table 45. synchronous uart ac timing specifications for recommended operating conditions, see ta bl e 3 characteristic symbol 1 min max unit notes outputs?internal clock delay t hikhov 01 1n s2 outputs?external clock delay t hekhov 11 4n s2 outputs?internal clock high impedance t hikhox 01 1n s2 outputs?external clock high impedance t hekhox 11 4n s2 inputs?internal clock input setup time t hiivkh 10 ? ns ? inputs?external clock input setup time t heivkh 8?n s? inputs?internal clock input hold time t hiixkh 0?n s? inputs?external clock input hold time t heixkh 1?n s? notes: 1. the symbols used for timing specifications follow the pattern t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t hikhox symbolizes the outputs internal timing (hi) for the time t serial memory clock reference (k) goes from the hi gh state (h) until outputs (o) are invalid (x). 2. output specifications are measured from the 50% level of the rising edge of clki n to the 50% level of the signal. timings are measured at the pin.
high-speed serdes interfaces (hssi) mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 77 the following figure provides the ac test load. figure 35. ac test load figure 36 and figure 37 represent the ac timing from table 44 and table 45 . note that although the specifications generally refer to the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. also note that the clock edge is selectable. the following figure shows the timing with external clock. figure 36. ac timing (external clock) diagram the following figure shows the timing with internal clock. figure 37. ac timing (internal clock) diagram 2.9 high-speed serdes interfaces (hssi) the mpc859e features a serializer/deserializer (serdes) interface to be used for high-speed serial interconnect applications.the serdes interface can be used for pci express and/or serial rapidio and/or sgmii data transfers. this section describes the common portion of serdes dc electrical specifications, wh ich is the dc requirement for serdes reference clocks. the serdes data lane?s transmitter (tx) and receiver (rx) reference circuits are also shown. output z 0 = 50 ov dd /2 r l = 50 serial clk (input) t heixkh t heivkh t hekhov t hekhox note: the clock edge is selectable. input signals: (see note) output signals: (see note) serial clk (output) t hiixkh t hikhov input signals: output signals: t hiivkh t hikhox
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 high-speed serdes interfaces (hssi) freescale semiconductor 78 2.9.1 signal terms definition the serdes utilizes differential signaling to transfer data across the serial link. th is section defines terms used in the desc ription and specification of differential signals. the below figure shows how the signals are defined. for illustration purposes only, one serdes lane is used in the description. the following figure shows the waveform for either a transmitter output (sd n _tx and sd n _tx ) or a receiver input (sd n _rx and sd n _rx ). each signal swings between a volts and b volts where a > b. figure 38. differential voltage definitions for transmitter or receiver using this waveform, the definitions are as shown in the follow ing list. to simplify the illustration, the definitions assume t hat the serdes transmitter and receiver operate in a fu lly symmetrical differenti al signaling environment: single-ended swing the transmitter output signals and th e receiver input signals sd_tx, sd_tx , sd_rx and sd_rx each have a peak-to-peak swing of a ? b volts. th is is also referred as each signal wire?s single-ended swing. differential output voltage, v od (or differential output swing ): the differential output voltage (or swing) of the transmitter, v od , is defined as the difference of the two complimentary output voltages: v sd_tx ? v sd_tx . the v od value can be either positive or negative. differential input voltage, v id (or differential input swing ): the differential input voltage (o r swing) of the receiver, v id , is defined as the difference of the two complimentary input voltages: v sd_rx ? v sd_rx . the v id value can be either positive or negative. differential peak voltage , v diffp the peak value of the differential transmitter output sign al or the differential receiver input signal is defined as the differential peak voltage, v diffp = |a ? b| volts. differential peak-to-peak , v diffp-p since the differential output signal of the transmitter and the differ ential input signal of the receiver each range from a ? b to ?(a ? b) volts, the peak -to-peak value of the differential transmitter output signal or the differential r eceiver input signal is defined as di fferential peak-to-peak voltage, v diffp-p = 2 v diffp = 2 |(a ? b)| volts, which is twice the differential swing in amplitude, or twice of the differential peak. fo r example, the output differentia l peak-peak voltage can also be calculated as v tx-diffp-p = 2 |v od |. differential waveform the differential waveform is constructed by subtracting the inverting signal (sd_tx , for example) from the non-inverting signal (sd_tx , for example) within a differen tial pair. there is only one differential swing, v id or v od = a ? b a volts b volts sd n _tx or sd n _rx sd n _tx or sd n _rx differential peak voltage, v diffp = |a ? b| differential peak-peak voltage, v diffpp = 2 * v diffp (not shown) v cm = (a + b)/2
high-speed serdes interfaces (hssi) mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 79 signal trace curve in a differential waveform. the voltage represente d in the differential waveform is not referenced to ground. see figure 43 as an example for differential waveform. common mode voltage, v cm the common mode voltage is equal to half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. in this example, for serdes output, v cm_out =(v sd_tx +v sd_tx ) 2 = (a + b) 2, which is the arithmetic mean of the two complimentary output voltages within a differenti al pair. in a system, the common mode voltage may often differ from one component?s output to th e other?s input. it may be different between the receiver input and driver output circuits within the same component. it is also referred to as the dc offset on some occasions. to illustrate these definitions using real values, consider th e example of a current mode logic (cml) transmitter that has a common mode voltage of 2.25 v and outputs, td and td . if these outputs have a swing from 2.0 v to 2.5 v, the peak-to-peak voltage swing of each signal (td or td ) is 500 mv p-p, which is referred to as the single-ended swing for each signal. because the differential signaling environment is fully symmetrical in this example, the transmitter output?s di fferential swing (v od ) has the same amplitude as each signal?s sing le-ended swing. the differential output signal ranges between 500 mv and ?500 mv. in other words, v od is 500 mv in one phase and ?500 mv in the other phase. the peak differential voltage (v diffp ) is 500 mv. the peak-to-peak differential voltage (v diffp-p ) is 1000 mv p-p. 2.9.2 serdes reference clocks the serdes reference clock inputs are appl ied to an internal pll whose output creates the clock used by the corresponding serdes lanes.the serdes reference clock inputs are sd_ref_clk and sd_ref_clk for pci express, serial rapidio, and sgmii interface, respectively. the following sections describe the serdes reference clock requirements and provide application information. 2.9.2.1 serdes spread spectrum clock source recommendations sd_ref_clk/sd_ref_clk are designed to work with spread spectrum clock for pci express protocol only with the spreading specification defined in table 46 . when using spread spectrum clocking fo r pci express, both ends of the link partners should use the same reference clock. for best results , a source without significant unintended modulation must be used . the spread spectrum clocking cannot be used if the same serd es reference clock is shared with other non-spread spectrum supported protocols. for example, if the spread spectrum clocki ng is desired on a serdes reference clock for pci express and the same reference clock is used for any other protocol such as sgmii/srio due to the serdes lane usage mapping option, spread spectrum clocking ca nnot be used at all. 2.9.2.2 serdes reference clock receiver characteristics the following figure shows a receiver referen ce diagram of the serdes reference clocks. table 46. serdes spread spectrum clock source recommendations at recommended operating conditions. see ta b l e 3 . parameter min max unit notes frequency modulation 30 33 khz ? frequency spread +0 ?0.5 % 1 note: 1. only down spreading is allowed.
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 high-speed serdes interfaces (hssi) freescale semiconductor 80 figure 39. receiver of serdes reference clocks the characteristics of the cl ock signals are as follows: ? the supply voltage requirements for xv dd are as specified in table 3 . ? the serdes reference clock receiver refe rence circuit structure is as follows: ? the sd_ref_clk and sd_ref_clk are internally ac-coupled di fferential inputs as shown in figure 39 . each differential clock input (sd_ref_clk or sd_ref_clk ) has a 50- termination to scoregnd followed by on-chip ac-coupling. ? the external reference clock driver must be able to drive this termination. ? the serdes reference clock input can be either diff erential or single-ended. s ee the differential mode and single-ended mode description below for further detailed requirements. ? the maximum average current requirement that also determines the common mode voltage range ? when the serdes reference clock differ ential inputs are dc-co upled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 ma. in this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximu m average current of 8 ma because the input is ac-coupled on-chip. ? this current limitation sets the maximum common mode input voltage to be less than 0.4 v (0.4 v 50 = 8 ma) while the minimum common mode input level is 0.1 v above scoregnd. for example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 to 16 ma (0?0.8 v), such that each phase of the differential input has a single-ended swing from 0 v to 800 mv with the common mode voltage at 400 mv. ? if the device driving the sd_ref_clk and sd_ref_clk inputs cannot drive 50 to scoregnd dc, or it exceeds the maximum input current limitations, then it must be ac-coupled off-chip. ? the input amplitude requirement ? this requirement is described in detail in the following sections. 2.9.2.3 dc level requirement for serdes reference clocks the dc level requirement for the serdes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and serdes reference clock inputs as described below. ? differential mode ? the input amplitude of the differential clock must be between 400 and 1600 mv differential peak-peak (or between 200 and 800 mv differential peak). in other words, each signal wire of the differential pair must have a single-ended swing less than 800 mv and greater than 200 mv. this requirem ent is the same for both external dc- or ac-coupled connections. input amp 50 50 sd_ref_clk sd_ref_clk
high-speed serdes interfaces (hssi) mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 81 ? for external dc-coupled connection, as described in section 2.9.2.2, ?serdes reference clock receiver characteristics,? the maximum average current re quirements sets the requirement for average voltage (common mode voltage) to be between 100 and 400 mv. the following figure shows the serdes reference clock input requirement for dc-coupled connection scheme. figure 40. differential reference clock input dc requirements (external dc-coupled) ? for external ac-coupled connection, there is no common mode voltage requirement for the clock driver. since the external ac-coupling capacitor blocks the dc level, the clock driver and the serdes reference clock receiver operate in different command mode voltages. the serdes reference clock receiver in this connection scheme has its common mode voltage set to scoregnd. each signal wire of the differential inputs is allowed to swing below and above the command mode voltage (scoregnd). the following figure shows the serdes reference clock input requirement for ac-coupled connection scheme. figure 41. differential reference clock input dc requirements (external ac-coupled) ? single-ended mode ? the reference clock can also be si ngle-ended. the sd_ref_clk input amplitude (single-ended swing) must be between 400 and 800 mv peak-peak (from v min to v max ) with sd_ref_clk either left unconn ected or tied to ground. ? the sd_ref_clk input average voltage must be between 200 and 400 mv. figure 42 shows the serdes reference clock input requirement for single-ended signaling mode. ? to meet the input amplitude requirement, the reference clock inputs might need to be dc- or ac-coupled externally. for the best noise performance, the reference of the clock could be dc- or ac-coupled into the unused phase (sd_ref_clk ) through the same source impedance as the clock input (sd_ref_clk) in use. sd_ref_clk sd_ref_clk v max < 800 mv v min > 0v 100 mv < v cm < 400 mv 200 mv < input amplitude or differential peak < 800 mv sd_ref_clk sd_ref_clk vcm 200 mv < input amplitude or differential peak < 800 mv vmax < vcm + 400 mv vmin > vcm ? 400 mv
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 high-speed serdes interfaces (hssi) freescale semiconductor 82 figure 42. single-ended reference clock input dc requirements 2.9.2.4 ac requirements for serdes reference clocks the following table lists ac re quirements for the pci express, sgmii, and serial rapidio serdes reference clocks to be guaranteed by the customer?s application design. table 47. sd_ref_clk and sd_ref_clk input clock requirements at recommended operating co nditions with scorevdd = 1.0 v 3%. and 1.1 v 3% parameter symbol min typ max unit notes sd_ref_clk/sd_ref_clk frequency range t clk_ref ?100/125? mhz 1 sd_ref_clk/sd_ref_clk clock frequency tolerance t clk_tol ?350 ? 350 ppm ? sd_ref_clk/sd_ref_clk reference clock duty cycle (measured at 1.6 v) t clk_duty 40 50 60 % 7 sd_ref_clk/sd_ref_clk max deterministic peak-peak jitter at 10 -6 ber t clk_dj ??42ps 7 sd_ref_clk/sd_ref_clk total reference clock jitter at 10 -6 ber (peak-to-peak jitt er at refclk input) t clk_tj ? ? 86 ps 2, 7 sd_ref_clk/sd_ref_clk rising/falling edge rate t clkrr/ t clkfr 1?4v/ns3, 7 sd_ref_clk sd_ref_clk 400 mv < sd_ref_clk input amplitude < 800 mv 0v
high-speed serdes interfaces (hssi) mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 83 figure 43. differential measurement points for rise and fall time figure 44. single-ended measurement points for rise and fall time matching differential input high voltage v ih 200 ? ? mv 4 differential input low voltage v il ? ? ?200 mv 4 rising edge rate (sd n_ ref_clk) to falling edge rate (sd n _ref_clk) matching rise-fall matching ??20%5, 6, 7 notes: 1. caution: only 100 and 125 have been tested . in-between values will not work correctly with the rest of the system. 2. limits from pci express cem rev 2.0 3. measured from ?200 mv to +200 mv on the differential waveform (derived from sd_ref_clk minus sd_ref_clk ). the signal must be monotonic through the measurement region for rise and fall ti me. the 400 mv measurement window is centered on the differential zero crossing. see figure 43 . 4. measurement taken from differential waveform 5. measurement taken from single-ended waveform 6. matching applies to rising edge for sd_ref_clk and falling edge rate for sd_ref_clk . it is measured using a 200 mv window centered on the median cross poin t where sd_ref_clk rising meets sd_ref_clk falling. the median cross point is used to calculate the voltage thresholds that the oscillosc ope uses for the edge rate calculations. the rise edge rate of sd_ref_clk must be compared to the fall edge rate of sd_ref_clk , the maximum allowed difference should not exceed 20% of the slowest edge rate. see figure 44 . 7. system/board must be designed to ensure the input requirem ent to the device is achieved. proper device operation is guaranteed for inputs meeting this r equirement by design, simulation, char acterization, or functional testing table 47. sd_ref_clk and sd_ref_clk input clock requirements (continued) at recommended operating co nditions with scorevdd = 1.0 v 3%. and 1.1 v 3% parameter symbol min typ max unit notes v ih = +200 mv v il = ?200 mv 0.0 v sd_ref_clk ? sd_ref_clk fall edge rate rise edge rate
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 pci express freescale semiconductor 84 2.9.2.5 serdes transmitter a nd receiver reference circuits the following figure shows the reference circuits for serdes data lane?s transmitter and receiver. figure 45. serdes transmitter a nd receiver reference circuits the dc and ac specification of serdes data lanes are defined in each interface protocol section (s gmii, pci express, or serial rapid io) in this document based on the application usage ? section 2.6.4, ?sgmii interf ace electrical characteristics? ? section 2.10, ?pci express? ? section 2.11, ?serial rapidio (srio)? note that external ac-coupling capacitor is required for the above three serial transmission protocols with the capacitor value defined in the specification of each protocol section. 2.9.2.6 clocking dependencies the ports on the two ends of a link must transmit data at a ra te that is within 600 parts per million (ppm) of each other at al l times. this is specified to allow bit rate clock sources with a 300 ppm tolerance. 2.10 pci express this section describes the dc and ac electrical speci fications for the pci expr ess bus of the mpc8569e. 2.10.1 pci express dc requirements for sd_ref_clk and sd_ref_clk for more information, see section 2.9.2.3, ?dc level requirement for serdes reference clocks.? 2.10.2 pci express dc physical layer specifications this section contains the dc specifications for th e physical layer of pci express on this device. 50 receiver transmitter sd_ tx n sd_txn sd_rx n sd_ rx n 50 50 50
pci express mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 85 2.10.2.1 pci express dc physical layer transmitter specifications this section discusses the pci express dc physical layer transmitter specifications for 2.5 gb/s. the following table defines the pci express (2.5 gb/s) dc specifications for the differential output at all transmitters. the parameters are specified at the component pins. 2.10.2.2 pci express dc physical layer receiver specifications this section discusses the pci express dc physical layer receiver specifications for 2.5 gb/s the following table defines the dc specifications for the pci expr ess (2.5 gb/s) differential input at all receivers (rxs). the parameters are specified at the component pins. table 48. pci express (2.5gb/s) differential transmitter (tx) output dc specifications at recommended operating conditions with xv dd = 1.0 v 3%. and 1.1 v 3% parameter symbol min typ max unit comments differential peak-to-peak output voltage v tx-diffp-p 800 1000 2 / 1100 3 1200 mv v tx-diffp-p = 2 |v tx-d+ ? v tx-d? | see note 1. de-emphasized differential output voltage (ratio) v tx-de-ratio 3.0 3.5 4.0 db ratio of the v tx-diffp-p of the second and following bits after a transition divided by the v tx-diffp-p of the first bit after a transition. see note 1. dc differential tx impedance z tx-diff-dc 80 100 120 tx dc differential mode low impedance transmitter dc impedance z tx-dc 40 50 60 required tx d+ as well as d? dc impedance during all states note: 1. specified at the measurement point into a timi ng and voltage compliance test load as shown in figure 46 and measured over any 250 consecutive tx uis. 2. typ-v tx-diffp-p with xv dd = 1.0 v 3. typ-v tx-diffp-p with xv dd = 1.1 v table 49. pci express (2.5 gb/s) differential receiver (rx) input dc specifications at recommended operating conditions with scorevdd = 1.0 v 3%. and 1.1 v 3% parameter symbol min typ max unit comments differential input peak-to-peak voltage v rx-diffp-p 175 ? 1200 mv v rx-diffp-p = 2 |v rx-d+ ? v rx-d? |. see note 1. dc differential input impedance z rx-diff-dc 80 100 120 rx dc differential mode impedance. see note 2.
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 pci express freescale semiconductor 86 2.10.3 pci express ac physical layer specifications this section contains the dc specifications for th e physical layer of pci express on this device. 2.10.3.1 pci express ac physical layer transmitter specifications this section discusses the pci express ac physical layer transmitter specifications for 2.5 gb/s. the following table defines the pci express (2.5gb/s) ac specifications fo r the differential output at all transmitters (txs). the parameters are specified at the component pins. the ac timing specifications do not include refclk jitter. dc input impedance z rx-dc 40 50 60 required rx d+ as well as d? dc impedance (50 20% tolerance). see notes 1 and 2. powered down dc input impedance z rx-high-imp-dc 50 ? ? ? required rx d+ as well as d? dc impedance when the receiver terminations do not have power. see note 3. electrical idle detect threshold v rx-idle-det- diffp-p 65 ? 175 mv v rx-idle-det-diffp-p = 2 |v rx-d+ ? v rx-d? |. measured at the package pins of the receiver. notes: 1. specified at the measurement point and measured over any 250 consecutive uis. the test load in figure 46 must be used as the rx device when taking measurements. if the clocks to th e rx and tx are not derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as a reference for the eye diagram. 2. impedance during all ltssm states. when transitioning from a fundamental reset to detect (the initial state of the ltssm) there is a 5 ms transition time before receiver terminatio n values must be met on all unconfigured lanes of a port. 3. the rx dc common mode impedance that exis ts when no power is present or fundamental reset is asserted. this helps ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. this term must be measured at 300 mv above the rx ground. table 50. pci express (2.5gb/s) differential transmitter (tx) output ac specifications at recommended operating conditions with xv dd = 1.0 v 3%. and 1.1 v 3% parameter symbol min typ max unit comments unit interval ui 399.88 400.00 400.12 ps each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. see note 1. minimum tx eye width t tx-eye 0.70 ? ? ui the maximum transmitter jitter can be derived as t tx-max-jitter = 1 ? t tx-eye = 0.3 ui. see notes 2 and 3. maximum time between the jitter median and maximum deviation from the median t tx-eye-median- to-max-jitter ? ? 0.15 ui jitter is defined as the measurement variation of the crossing points (v tx-diffp-p = 0 v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. see notes 2 and 3. table 49. pci express (2.5 gb/s) differential r eceiver (rx) input dc specifications (continued) at recommended operating conditions with scorevdd = 1.0 v 3%. and 1.1 v 3% parameter symbol min typ max unit comments
pci express mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 87 2.10.3.2 pci express ac physical layer receiver specifications this section discusses the pci express ac phys ical layer receiver specifications for 2.5 gb/s. ac-coupling capacitor c tx 75 ? 200 nf all transmitters are ac-coupled. the ac-coupling is required either within the media or within the transmitting component itself. see note 4. notes: 1. no test load is necessarily associated with this value. 2. specified at the measurement point into a ti ming and voltage compliance test load as shown in figure 46 and measured over any 250 consecutive tx uis. 3. a t tx-eye = 0.70 ui provides for a total sum of det erministic and random jitter budget of t tx-jitter-max = 0.30 ui for the transmitter collected over any 250 consecutive tx uis. the t tx-eye-median-to-max-jitter median is less than half of the total tx jitter budget collected over any 250 consecutive tx uis. it must be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as oppose d to the averaged time value. 4. the mpc8569e serdes transmitter does not have ctx built-in. an external ac-coupling capacitor is required. table 50. pci express (2.5gb/s) differential transmitter (tx) output ac specifications (continued) at recommended operating conditions with xv dd = 1.0 v 3%. and 1.1 v 3% parameter symbol min typ max unit comments
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 pci express freescale semiconductor 88 the following table defines the ac specifications for the pci express (2.5 gb/s) differential input at all receivers (rxs). the parameters are specified at the component pins. the ac timing specifications do not include refclk jitter. table 51. pci express (2.5 gb/s) differential receiver (rx) input ac specifications at recommended operating conditions with scorevdd = 1.0 v 3%. and 1.1 v 3% parameter symbol min typ max unit comments unit interval ui 399.88 400.00 400.12 ps each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. see note 1. minimum receiver eye width t rx-eye 0.4 ? ? ui the maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as t rx-max-jitter = 1 ? t rx-eye = 0.6 ui. see notes 2 and 3. maximum time between the jitter median and maximum deviation from the median. t rx-eye-media n-to-max-jitter ? ? 0.3 ui jitter is defined as the measurement variation of the crossing points (v rx-diffp-p = 0 v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. see notes 2, 3, and 4. notes: 1. no test load is necessarily associated with this value. 2. specified at the measurement point and measured over any 250 consecutive uis. the test load in figure 46 must be used as the rx device when taking measurements. if the clocks to the rx and tx are not derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as a reference for the eye diagram. 3. a t rx-eye = 0.40 ui provides for a total sum of 0.60 ui deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive uis. the t rx-eye-median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. ui jitter budget collected over any 250 consecutive tx uis. it must be noted that the median is not the same as the mean. the ji tter median describes the point in time where the number of jitter points on either side is app roximately equal as opposed to the averaged time value. if the clocks to the rx and tx are not derived from the same referenc e clock, the tx ui recovered from 3500 consecutive ui must be used as the reference for the eye diagram. 4. it is recommended that the recovered tx ui is calculated using all edges in the 35 00 consecutive ui interval with a fit algor ithm using a minimization merit function. least squares and medi an deviation fits have worked well with experimental and simulated data.
serial rapidio (srio) mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 89 2.10.4 compliance test and measurement load the ac timing and voltage parameters must be verified at the measurement point. the package pins of the device must be connected to the test/measurement load within 0.2 inches of that load, as shown in the following figure. note the allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from d+ and d? not being exactly matched in length at the package pin boundary. if the vendor does not explicitly state where the measurement point is located, the measurement point is assumed to be the d+ and d? package pins. figure 46. compliance test/measurement load 2.11 serial rapidio (srio) this section describes the dc and ac electrical specifications for the serial rapidio inte rface of the mpc8569e, for the lp-serial physical layer. the electrical specifications cover both single- and multiple-lane links. two transmitters (short and long run) and a single receiver are specified for each of three baud rates, 1. 25, 2.50, and 3.125 gbaud. two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to driving two connectors across a backplane. a single receiver specification is given that will accept signals from both the short- and long-run transmi tter specifications. the short-run transmitter must be used mainly for chip-to-chip connections on either the same printed-circuit board or across a single connector. this covers the case wh ere connections are made to a mezzanine (daughter) card. the mini mum swings of the short-run specification reduce the overall power used by the transceivers. the long-run transmitter specificat ions use larger voltage swings that are capab le of driving signals across backplanes. this allows a user to drive signals across two connectors and a backplane. th e specifications allow a distance of at least 50 cm at all baud rates. all unit intervals are specified with a tolerance of 100 ppm. the worst case freq uency difference betw een any transmit and receive clock is 200 ppm. to ensure interoperability between drivers and receivers of di fferent vendors and technologies, ac-coupling at the receiver inp ut must be used.signal definitions 2.11.1 signal definitions this section defines terms used in the description and specification of differential signals used by the lp-serial links. figure 47 shows how the signals are defined. the figures show waveforms for either a transmitter output (td and td ) or a receiver input tx silicon + package c = c tx c = c tx r = 50 r = 50 d+ package pin d? package pin d+ package pin
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 serial rapidio (srio) freescale semiconductor 90 (rd and rd ). each signal swings between a volts and b volts wher e a > b. using these waveforms, the definitions are as follows: 1. the transmitter output signals and the receiver input signals td, td , rd, and rd each have a peak-to-peak swing of a ? b volts 2. the differential output signal of the transmitter, v od , is defined as v td ? v td 3. the differential input signal of the receiver, v id , is defined as v rd ? v rd 4. the differential output signal of the tr ansmitter and the differential input signal of the receiver each range from a ? b to ?(a ? b) volts 5. the peak value of the differential tran smitter output signal and th e differential receiver input signal is a ? b volts 6. the peak-to-peak value of the differential transm itter output signal and the differen tial receiver input signal is 2 (a ? b) volts figure 47. differential peak-peak voltage of transmitter or receiver to illustrate these definitions using real values, consider the case of a cml (current mode lo gic) transmitter that has a commo n mode voltage of 2.25 v and each of its outputs, td and td , has a swing that goes between 2.5 and 2.0 v. using these values, the peak-to-peak voltage swing of the signals td and td is 500 mv p-p. the differential output signal ranges between 500 and ?500 mv. the peak differential voltag e is 500 mv. the peak-to-peak diff erential voltage is 1000 mv p-p. 2.11.2 equalization with the use of high speed serial links, the interconnect media wi ll cause degradation of the sign al at the receiver. effects s uch as inter-symbol interference (isi ) or data dependent jitter are produced. this loss can be large enough to degrade the eye open ing at the receiver beyond what is allowed in the specification. to negate a portion of these effects, equalization can be used. th e most common equalizat ion techniques that can be used are: ? pre-emphasis on the transmitter ? a passive high pass filter network placed at the receiver. this is often referred to as passive equalization. ? the use of active circuits in the receiver. this is often referred to as adaptive equalization. differential peak-to-peak = 2 (a ? b) a volts td or rd td or rd b volts
serial rapidio (srio) mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 91 2.11.3 dc requirements for serial rapidio this section explains the dc requirem ents for the serial rapidio interface. 2.11.3.1 dc requirements for serial rapidio sd_ref_clk and sd_ref_clk the characteristics and dc requirements of the separate serdes reference clocks of the srio interface are described in section 2.9.2.3, ?dc level requirem ent for serdes reference clocks.? 2.11.3.2 dc serial rapidio timi ng transmitter specifications the lp-serial transmitter electrical and timing sp ecifications are given in the following sections. the differential return loss, s11, of the transm itter in each case are better than the following: ? ?10 db for (baud frequency) 10 < freq(f) < 625 mhz ? ?10 db + 10log(f 625 mhz) db for 625 mhz freq(f) baud frequency the reference impedance for the differenti al return loss m easurements is 100- resistive. differentia l return loss includes contributions from on-chip circuitry, chip packaging, and any off-chip components related to the driver. the output impedance requirement applies to all valid output levels. it is recommended that the 20%?80% rise/fall time of the tran smitter, as measured at the transmitter output, in each case have a minimum value 60 ps. it is recommended that the timing skew at the output of an lp-serial transmitter between the two signals that comprise a differential pair not exceed 25 ps at 1.25 gb, 20 ps at 2. 50 gb, and 15 ps at 3.125 gb. the following table defines the serial rapidio transmitter dc specifications. 2.11.3.3 dc serial rapidi o receiver specifications the lp-serial receiver electrical and timing specifications are given in the following sections. receiver input impedance shall result in a differential return loss better that 10 db and a common mode return loss better than 6 db from 100 mhz to (0.8) (baud frequency). this includes contributions from on-chip circuitry, the chip package, and any off-chip components related to the receiver. ac coupling components are included in this requirement. the reference impedance for return loss measurements is 100- resistive for differential return loss and 25- resistive for common mode. table 52. srio transmitter dc timing specifications?1.25, 2.5, and 3.125 gbauds at recommended operating conditions with xv dd = 1.0 v 3%. and 1.1 v 3% parameter symbol min typ max unit notes output voltage v o ?0.40 ? 2.30 v 1 long-run differential output voltage v diffpp 800 ? 1600 mv p-p ? short-run differential output voltage v diffpp 500 ? 1000 mv p-p ? note: 1. voltage relative to common of either signal comprising a differential pair.
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 serial rapidio (srio) freescale semiconductor 92 the following table defines the serial rapidio receiver dc specifications. 2.11.4 ac requirements for serial rapidio this section explains the ac require ments for the serial rapidio interface. 2.11.4.1 ac requirements for serial rapidio sd_ref_clk and sd_ref_clk note that the serial rapidio clock requirements for sd n _ref_clk and sd n _ref_clk are intended to be used within the clocking guidelines specified by section 2.9.2.4, ?ac requirements for serdes reference clocks.? table 53. srio receiver dc timing specifications?1.25 gbaud, 2.5 gbaud, 3.125 gbaud at recommended operating conditions with sc orevdd = 1.0 v 3%. and 1.1 v 3%. parameter symbol min typ max unit notes differential input voltage v in 200 ? 1600 mv p-p 1 note: 1. measured at receiver
serial rapidio (srio) mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 93 2.11.4.2 ac requirements for serial rapidio transmitter the following table defines the transmitter ac specifications for the serial rapidio. the ac timing specifications do not include refclk jitter the following table defines the receiver ac specifications for serial rapidio. the ac timing specifications do not include refclk jitter. table 54. srio transmitter ac timing specifications at recommended operating conditions with xv dd = 1.0 v 3%. and 1.1 v 3% parameter symbol min typical max unit notes deterministic jitter j d ? ? 0.17 ui p-p ? total jitter j t ? ? 0.35 ui p-p ? unit interval: 1.25 gbaud ui 800 ? 100ppm 800 800 + 100ppm ps ? unit interval: 2.5 gbaud ui 400 ? 100ppm 400 400 + 100ppm ps ? unit interval: 3.125 gbaud ui 320 ? 100ppm 320 320 + 100ppm ps ? table 55. srio receiver ac timing specifications at recommended operating conditions with scorevdd = 1.0 v 3%. and 1.1 v 3%. parameter symbol min typical max unit notes deterministic jitter tolerance j d 0.37 ? ? ui p-p 1, 3 combined deterministic and random jitter tolerance j dr 0.55 ? ? ui p-p 1, 3 total jitter tolerance 2 j t 0.65 ? ? ui p-p 1, 3 bit error rate ber ? ? 10 ?12 ?? unit interval: 1.25 gbaud ui 800 ? 100ppm 800 800 + 100ppm ps ? unit interval: 2.5 gbaud ui 400 ? 100ppm 400 400 + 100ppm ps ? unit interval: 3.125 gbaud ui 320 ? 100ppm 320 320 + 100ppm ps ? notes : 1. measured at receiver 2. total jitter is composed of three components: deterministic jitter, random jitter and single frequency sinusoidal jitter. th e sinusoidal jitter may have any amplitude and frequency in the unshaded region of figure 48 . the sinusoidal jitter component is included to ensure margin for low-frequency jitter, wande r, noise, crosstalk, and other variable system effects. 3. system/board must be designed to ensure the input requirement to the device is achieved. proper device operation is guaranteed for inputs meeting this requ irement by design, simulation, characterization, or functional testing
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 i 2 c freescale semiconductor 94 figure 48. single frequency sinusoidal jitter limits 2.12 i 2 c this section describes the dc and ac electrical character istics for the i 2 c interfaces of the mpc8569e. 2.12.1 i 2 c dc electrical characteristics the following table provides the dc electrical character istics for the i 2 c interface. table 56. i 2 c dc electrical characteristics for recommended operating conditions, see ta bl e 3 parameter symbol min max unit notes input high voltage v ih 2?v1 input low voltage v il ?0 . 8v1 output low voltage (ov dd = min, i ol = 2 ma) v ol 00 . 4v2 8.5 ui p-p 0.10 ui p-p sinusoidal jitter amplitude 22.1 khz 1.875 mhz 20 mhz frequency
i 2 c mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 95 2.12.2 i 2 c ac electrical specifications the following table provides the ac timing parameters for the i 2 c interface. pulse width of spikes that must be suppressed by the input filter t i2khkl 05 0n s3 input current each i/o pin (i nput voltage is between 0.1 ov dd and 0.9 ov dd (max) ) i i ?10 10 a4 capacitance for each i/o pin c i ?1 0p f? notes: 1. the min v il and max v ih values are based on the respective min and max ov in values found in ta b l e 3 . 2. output voltage (open drain or open co llector) condition = 3 ma sink current. 3. see the mpc8569e powerquicc iii integrated processor family reference manual for information about the digital filter used. 4. i/o pins obstruct the sda and scl lines if ov dd is switched off. table 57. i 2 c ac timing specifications at recommended operating conditions with ov dd of 3.3 v 5% parameter symbol 1 min max unit notes scl clock frequency f i2c 04 0 0k h z2 low period of the scl clock t i2cl 1.3 ? s? high period of the scl clock t i2ch 0.6 ? s? setup time for a repeated start condition t i2svkh 0.6 ? s? hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl 0.6 ? s? data setup time t i2dvkh 100 ? ns ? data input hold time: cbus compatible masters i 2 c bus devices t i2dxkl ? 0 ? ? s3 data output delay time t i2ovkl ?0 . 9 s4 setup time for stop condition t i2pvkh 0.6 ? s? bus free time between a stop and start condition t i2khdx 1.3 ? s? table 56. i 2 c dc electrical characteristics (continued) for recommended operating conditions, see ta bl e 3 parameter symbol min max unit notes
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 i 2 c freescale semiconductor 96 the following figure provides the ac test load for the i 2 c. figure 49. i 2 c ac test load the following figure shows the ac timing diagram for the i 2 c bus. figure 50. i 2 c bus ac timing diagram noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd ?v? noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd ?v? capacitive load for each bus line cb ? 400 pf ? notes: 1. the symbols used for timing specificat ions herein follow the pattern t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c timing (i2) for the time that the data with respect to the stop condition (p) reaches the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. 2. the requirements for i 2 c frequency calculation must be followed. see fr eescale application note an 2919, ?determining the i2c frequency divider ratio for scl.? 3. as a transmitter, the mpc8659e provides a delay time of at least 300 ns for the sda signal (referred to as the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl to avoid unintended generation of a start or stop condition. when the mpc8569e acts as the i 2 c bus master while transmitting, it driv es both scl and sda. as long as the load on scl and sda are balanced, the mpc8569e does not generate an unintended start or stop condition. therefore, the 300 ns sda output delay time is not a concern. if under some rare condition, the 300 ns sda output delay time is required for the mpc8569e as transmitter, application note an2919, referred to in note 4 below, is recommended. 4. the maximum t i2ovkl must be met only if the device does not stretch the low period (t i2cl ) of the scl signal. table 57. i 2 c ac timing specifications (continued) at recommended operating conditions with ov dd of 3.3 v 5% parameter symbol 1 min max unit notes output z 0 = 50 ov dd /2 r l = 50 sr s sda scl t i2sxkl t i2cl t i2ch t i2dxkl, t i2ovkl t i2dvkh t i2sxkl t i2svkh t i2khkl t i2pvkh ps t i2khdx
gpio mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 97 2.13 gpio this section describes the dc and ac electrical characteristics for the gpio interface. 2.13.1 gpio dc electrical characteristics the following table provides the dc electri cal characteristics for the gpio interface when operating from a 3.3 v supply 2.13.2 gpio ac timing specifications the following table provides the gpio input and output ac timing specifications. the following figure provides the ac test load for the gpio. figure 51. gpio ac test load table 58. gpio dc electrical characteristics (3.3 v) for recommended operating conditions, see ta b l e 3 parameter symbol min max unit notes input high voltage v ih 2?v 1 input low voltage v il ?0 . 8 v 1 input current (ov in = 0 v or ov in = ov dd ) i in ? 4 0 a2 output high voltage (ov dd = min, i oh = ?2 ma) v oh 2.4 ? v ? output low voltage (ov dd = min, i ol = 2 ma) v ol ?0 . 4 v ? note: 1. the min v il and max v ih values are based on the min and max ov in respective values found in ta b l e 3 . 2. the symbol ov in represents the input voltage of the supply. it is referenced in ta bl e 3 . table 59. gpio input ac timing specifications for recommended operating conditions, see ta b l e 3 parameter symbol min unit notes gpio inputs?minimum pulse width t piwid 20 ns 1 notes: 1 . gpio inputs and outputs are asynchronous to any visible cl ock. gpio outputs must be synchronized before use by any external synchronous logic. gpio inputs are required to be valid for at least t piwid to ensure proper operation. output z 0 = 50 ov dd /2 r l = 50
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 jtag controller freescale semiconductor 98 2.14 jtag controller this section describes the dc and ac electrical specifications for the ieee 1149.1 (jtag) interface. 2.14.1 jtag dc electrical characteristics the following table provides the jtag dc electrical characteristics. 2.14.2 jtag ac timing specifications the following table provides the jtag ac timing specifications as defined in figure 52 through figure 55 . table 60. jtag dc electrical characteristics for recommended operating conditions, see ta bl e 3 parameter symbol min max unit notes input high voltage v ih 2?v 1 input low voltage v il ?0 . 8 v 1 input current (ov in = 0 v or ov in = ov dd ) i in ? 4 0 a2 output high voltage (ov dd = min, i oh = ?2 ma) v oh 2.4 ? v ? output low voltage (ov dd = min, i ol = 2 ma) v ol ?0 . 4 v ? note: 1. the min v il and max v ih values are based on the respective min and max ov in values found in ta b l e 3 . 2. the symbol ov in represents the input voltage of th e supply. it is referenced in ta b l e 3 . table 61. jtag ac timing specifications for recommended operating conditions, see ta bl e 3 parameter symbol 1 min max unit notes jtag external clock frequency of operation f jtg 03 3 . 3m h z? jtag external clock cycle time t jtg 30 ? ns ? jtag external clock pulse width measured at 1.4 v t jtkhkl 15 ? ns ? jtag external clock rise and fall times t jtgr /t jtgf 02n s4 trst assert time t trst 25 ? ns 2 input setup times t jtdvkh 4?n s?
jtag controller mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 99 the following figure provides the ac test load for tdo an d the boundary-scan outputs of the device. figure 52. ac test load for the jtag interface the following figure provides the jtag clock input timing diagram. figure 53. jtag clock input timing diagram the following figure provides the trst timing diagram. figure 54. trst timing diagram input hold times t jtdxkh 10 ? ns ? output valid times: boundary-scan data tdo t jtkldv ? ? 15 10 ns 3 output hold times t jtkldx 0?n s3 notes: 1. the symbols used for timing spec ifications follow the pattern t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time dat a input signals (d) reaching the va lid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) reaching the invalid state (x) relative to the t jtg clock reference (k) going to the high (h) state. note that in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 3. all outputs are measured from the mi dpoint voltage of the falling edge of t tclk to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50- load. time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 4. system/board must be designed to ensure the input requirement to the device is achieved. proper device operation is guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing table 61. jtag ac timing specifications (continued) for recommended operating conditions, see ta bl e 3 parameter symbol 1 min max unit notes output z 0 = 50 ov dd /2 r l = 50 jtag t jtkhkl t jtgr external clock vm vm vm t jtg t jtgf vm = midpoint voltage (ov dd /2) trst vm = midpoint voltage (ov dd /2) vm vm t trst
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 enhanced local bus controller freescale semiconductor 100 the following figure provides the boundary-scan timing diagram. figure 55. boundary-scan timing diagram 2.15 enhanced local bus controller this section describes the dc and ac electrical specifications for the enhanced local bu s interface of the mpc8569e. 2.15.1 enhanced local bus dc electrical characteristics the following table provides the dc elect rical characteristics for the enhanced local bus interface when operating at bv dd = 3.3 v dc. table 62. enhanced local bus dc electrical characteristics (3.3 v dc) for recommended operating conditions, see ta bl e 3 parameter symbol min max unit notes input high voltage v ih 2?v1 input low voltage v il ?0 . 8v1 input current (v in = 0 v or v in = bv dd )i in ? 4 0 a2 output high voltage (bv dd = min, i oh = ?2 ma) v oh 2.4 ? v ? output low voltage (bv dd = min, i ol = 2 ma) v ol ?0 . 4v? note: 1. the min v il and max v ih values are based on the respective min and max bv in values found in ta b l e 3 2. the symbol v in , in this case, represents the bv in symbol referenced in section 2.1.1.1, ?recommended operating conditions .? vm = midpoint voltage (ov dd /2) vm vm t jtdvkh t jtdxkh boundary data outputs jtag external clock boundary data inputs output data valid t jtkldx t jtkldv input data valid
enhanced local bus controller mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 101 the following table provides the dc elect rical characteristics for the enhanced local bus interface when operating at bv dd = 2.5 v dc. the following table provides the dc elect rical characteristics for the enhanced local bus interface when operating at bv dd = 1.8 v dc. 2.15.2 enhanced local bus ac electrical specifications this section describes the ac timing specifi cations for the enhanced local bus interface. 2.15.2.1 test condition the following figure provides the ac test load for the enhanced local bus. figure 56. enhanced local bus ac test load table 63. enhanced local bus dc electrical characteristics (2.5 v dc) for recommended operating conditions, see ta bl e 3 parameter symbol min max unit notes input high voltage v ih 1.70 ? v 1 input low voltage v il ?0 . 7v1 input current (v in = 0 v or v in = bv dd )i in ? 4 0 a2 output high voltage (bv dd = min, i oh = ?1 ma) v oh 2.0 ? v ? output low voltage (bv dd = min, i ol = 1 ma) v ol ?0 . 4v? note: 1. the min v il and max v ih values are based on the respective min and max bv in values found in ta b l e 3 2. the symbol v in , in this case, represents the bv in symbol referenced in section 2.1.1.1, ?recommended operating conditions .? table 64. enhanced local bus dc electrical characteristics (1.8 v dc) for recommended operating conditions, see ta bl e 3 parameter symbol min max unit notes input high voltage v ih 1.25 ? v 1 input low voltage v il ?0 . 6v1 input current (v in = 0 v or v in = bv dd )i in ? 4 0 a2 output high voltage (bv dd = min, i oh = ?0.5 ma) v oh 1.35 ? v ? output low voltage (bv dd = min, i ol = 0.5 ma) v ol ?0 . 4v? note: 1. the min v il and max v ih values are based on the respective min and max bv in values found in ta b l e 3 2. the symbol v in , in this case, represents the bv in symbol referenced in section 2.1.1.1, ?recommended operating conditions .? output z 0 = 50 bv dd /2 r l = 50
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 enhanced local bus controller freescale semiconductor 102 2.15.2.2 enhanced local bus ac timing specifications for pll enable mode for pll enable mode, all timings are re lative to the rising edge of lsync_in. the following table describes the timing specifica tions of the enhanced local bus interface at bv dd = 3.3 v, 2.5 v and 1.8 v for pll enable mode. table 65. enhanced local bus timing specifications (bv dd = 3.3 v 2.5 v and 1.8 v) ?pll enabled mode for recommended operating conditions, see ta b l e 3 parameter symbol 1 min max unit notes enhanced local bus cycle time t lbk 7.5 12 ns ? enhanced local bus duty cycle t lbkh/ t lbk 45 55 % 5 lclk[n] skew to lclk[m] or lsync_out t lbkskew ? 680 ps 2 input setup t lbivkh 2?n s? input hold t lbixkh 1.0 ? ns ? output delay (except lale) t lbkhov ?3 . 8n s? output hold (except lale) t lbkhox 0.6 ? ns ? enhanced local bus clock to output high impedance for lad/ldp t lbkhoz ?3 . 8n s3 lale output negation to lad/ldp output transition (latch hold time) t lbonot 1 ? 0.475 ns (lbcr[ahd]=0) ? ? 0.475 ns (lbcr[ahd] = 1) ? elbc controller clock cycle (= 1 platform clock cycle in ns) 4 notes: 1. all signals are measured from bv dd /2 of the rising edge of lsync_in to bv dd /2 of the signal in question. 2. skew measured between different lclk signals at bv dd /2. 3. for purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. t lbonot is a measurement of the minimum time between the negation of lale and any change in lad. t lbonot is determined by lbcr[ahd]. the unit is the elbc controller clock cycle. the elbc controller clock refers to the internal clock that runs the local bus controller, not the external lc lk. lclk cycle = elbc controller clock cycle lcrr[clkdiv]. after power on reset, lbcr[ahd] defaults to 0 and elbc runs at maximum hold time. 5. system/board must be designed to ensure the input requirement to the device is achieved. proper device operation is guaranteed for inputs meeting this requi rement by design, simulation, characterization, or functional testing.
enhanced local bus controller mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 103 the following figure shows the ac timing diagram for pll-enabled mode. figure 57. local bus ac timing diagram (pll enabled) the above figure applies to all three contro llers that elbc supports : gpcm, upm and fcm. for input signals, the ac timing data is used directly for all three controllers. t lbkhox lsync_in input signals output signal lale t lbixkh1 t lbivkh1 t lbonot t lbkhov (except lale) lad (address phase) lad/ldp (data phase) t lbkhoz
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 enhanced local bus controller freescale semiconductor 104 for output signals, each type of controller provides its own uniq ue method to control the signal timing. the fina l signal delay value for output signals is the programmed delay plus the ac timing delay. for example, for gpcm, lcs can be programmed to delay by t acs (0, ?, ?, 1, 1 + ?, 1 + ?, 2, 3 cycles), so the final delay is t acs + t lbkhov . the following figure shows how the ac timing diagram applies to gpcm. the same principle applies to upm and fcm. figure 58. gpcm output timing diagram (pll enabled) 2.15.2.3 enhanced local bus ac timi ng specifications for pll bypass mode all output signal timings are relative to the falling edge of any lclks for pll bypass mode. the external circuit must use the rising edge of the lclks to latch the data. all input timings except lupwait/lfrb are relative to the rising edge of lclks. lupwait/lfrb are relative to the falling edge of lclks. t arcs +t lbkhov lsync_in lad[0:31] lbctl t lbonot lcs_b lgpl2/loe_b address t addr t aoe +t lbkhov lwe_b t awcs +t lbkhov t lbonot address t addr t awe +t lbkhov t lbkhox t rc t oen read data write data t wen t wc write read lale 1 t addr is programmable and determined by lcrr[eadc] and orx[ead]. 2 t arcs , t awcs , t aoe , t rc , t oen , t awe , t wc , t wen are determined by orx. refer to reference manual.
enhanced local bus controller mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 105 the following table describes the timing specifica tions of the enhanced local bus interface at bv dd = 3.3, 2.5, and 1.8 v dc with pll disabled. table 66. enhanced local bus timing specifications (bv dd = 3.3 v, 2.5 v, and 1.8 v)?pll bypassed for recommended operating conditions, see ta bl e 3 parameter symbol 1 min max unit notes enhanced local bus cycle time t lbk 12 ? ns ? enhanced local bus duty cycle t lbkh /t lbk 45 55 % 6 lclk[n] skew to lclk[m] or lsync_out t lbkskew ?1 5 0p s2 input setup (except lupwait/lfrb) t lbivkh 6.5 ? ns ? input hold (except lupwait/lfrb) t lbixkh 1?n s? input setup (for lupwait/lfrb) t lbivkl 6.5 ? ns ? input hold (for lupwait/lfrb) t lbixkl 1?n s? output delay (except lale) t lbklov ?1 . 5n s? output hold (except lale) t lbklox ?3.5 ? ns 5 enhanced local bus clock to output high impedance for lad/ldp t lbkloz ?2n s3 lale output negation to lad/ldp output transition (latch hold time) t lbonot 1 ? 1 ns (lbcr[ahd] = 0) 1/2 ? 1 ns (lbcr[ahd] = 1) ? elbc controller clock cycle (=1 platform clock cycle in ns) 4 notes: 1. all signals are measured from bv dd /2 of rising/falling edge of lclk to bv dd /2 of the signal in question. 2. skew measured between different lclk signals at bv dd /2. 3. for purposes of active/float timing measurements, the high impe dance or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. t lbonot is a measurement of the minimum time between the negation of lale and any change in lad. t lbonot is determined by lbcr[ahd]. the unit is the elbc controller clock cycle, which is the internal clock that runs the local bus controller, not the external lclk. lclk cycle = elbc controller clock cycle lcrr[clkdiv]. after power on reset, lbcr[ahd] defaults to 0 and elbc runs at maximum hold time. 5. output hold is negative. this means that output transit ion happens earlier than the falling edge of lclk. 6. system/board must be designed to ensure the input requirement to the device is achieved. proper device operation is guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 enhanced local bus controller freescale semiconductor 106 the following figure shows the ac timing diagram for pll bypass mode. figure 59. enhanced local bus signals (pll bypass mode) the above figure applies to all three controll ers that elbc supports: gpcm, upm, and fcm. for input signals, the ac timing data is used directly for all three controllers. for output signals, each type of controller provides its own uniq ue method to control the signal timing. the fina l signal delay value for output signals is the programmed delay plus the ac timing delay. for example, for gpcm, lcs can be programmed to delay by t acs (0, ?, ?, 1, 1 + ?, 1 + ?, 2, 3 cycles), so the final delay is t acs + t lbkhov . output signals t lbklox lclk[m] input signals lale t lbixkh t lbivkh t lbivkl t lbixkl input signal t lbonot (lupwait/lfrb) (except lupwait/lfrb) (except lale) lad (address phase) lad/ldp (data phase) t lbkloz t lbklov
enhanced secure digital host controller (esdhc) mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 107 the following figure shows how the ac timing diagram applies to gpcm in pll bypass mode. the same principle applies to upm and fcm. figure 60. gpcm output timing diagram (pll bypass mode) 2.16 enhanced secure digita l host controller (esdhc) this section describes the dc and ac electrical sp ecifications for the esdhc interface of the mpc8569e. 2.16.1 esdhc dc electrical characteristics the following table provides the dc electrical characteristi cs for the esdhc inte rface of the mpc8569e. table 67. esdhc interface dc electrical characteristics at recommended operating conditions with ov dd =3.3v characteristic symbol condition min max unit notes input high voltage v ih ?0 . 6 2 5 ov dd ?v1 input low voltage v il ? ? 0.25 ov dd v1 output high voltage v oh i oh = ?100 a at ov dd min 0.75 ov dd ?v? output low voltage v ol i ol = 100 a at ov dd min ? 0.125 ov dd v? t arcs +t lbkhov lclk lad[0:31] lbctl t lbonot lcs_b lgpl2/loe_b address t addr t aoe +t lbkhov lwe_b t awcs +t lbkhov t lbonot address t addr t awe +t lbkhov t lbkhox t rc t oen read data write data t wen t wc write read lale 1 t addr is programmable and determined by lcrr[eadc] and orx[ead]. 2 t arcs , t awcs , t aoe , t rc , t oen , t awe , t wc , t wen are determined by orx. refer to the mpc8569e reference manual.
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 enhanced secure digital host controller (esdhc) freescale semiconductor 108 2.16.2 e sdhc ac timing specifications the following table provides the esdhc ac timing specifications as defined in figure 61 and figure 62 . output high voltage v oh i oh = ?100 aov dd ?0.2 ? v 2 output low voltage v ol i ol = 2 ma ? 0.3 v 2 input/output leakage current i in /i oz ?? 1 01 0 a? note: 1. the min v il and max v ih values are based on the respective min and max ov in values found in ta bl e 3 . 2. open drain mode for mmc cards only. table 68. esdhc ac timing specifications at recommended operating conditions with ov dd =3.3v parameter symbol 1 min max unit notes sd_clk clock frequency: sd/sdio full speed/high speed mode mmc full speed/high speed mode f shsck 0 25/50 20/52 mhz 2, 4 sd_clk clock low time?high speed/full speed mode t shsckl 7/10 ? ns 4 sd_clk clock high time?high speed/full speed mode t shsckh 7/10 ? ns 4 sd_clk clock rise and fall times t shsckr/ t shsckf ? 3 ns 4, 5 input setup times: sd_cmd, sd_datx, sd_cd to sd_clk t shsivkh 3.7 ? ns 3, 4, 6 input hold times: sd_cmd, sd_datx, sd_cd to sd_clk t shsixkh 2.5 ? ns 4, 6 output delay time: sd_clk to sd_cmd, sd_datx valid t shskhov ?3 3 ns 4, 6 notes: 1. the symbols used for timing specifications follow the pattern t (first three letters of functional block)(signal)(state)(reference)(state) for inputs and t (first three letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t fhskhov symbolizes esdhc high speed mode device timing (shs) clock reference (k) going to th e high (h) state, with respect to the output (o) reaching the invalid state (x) or output hold time. note that in general, t he clock reference symbol representation is based on five letters representing the clock of a particular functional. for rise and fa ll times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. in full speed mode, clock frequency value can be 0?25 mhz for a sd/sdio card and 0?20 mhz for a mmc card. in high speed mode, clock frequency value can be 0?50 mhz for a sd/sdio card and 0?52 mhz for a mmc card. 3. to satisfy setup timing, one way board routing delay between host and card, on sd_clk, sd_cmd and sd_datx should not exceed 0.65ns. 4. ccard 10 pf, (1 card) and c l = c bus + c host +c card 40 pf. 5. system/board must be designed to ensure the input requirement to the device is achieved. proper device operation is guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing. 6. the parameter values apply to both full speed and high speed modes. table 67. esdhc interface dc electr ical characteri stics (continued) at recommended operating conditions with ov dd =3.3v characteristic symbol condition min max unit notes
timers mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 109 the following figure provides the esdhc clock input timing diagram. figure 61. esdhc clock input timing diagram the following figure provides the data and command input/output timing diagram. figure 62. esdhc data and command input/out put timing diagram referenced to clock 2.17 timers this section describes the dc and ac electrical specifications for the timers of the mpc8569e. 2.17.1 timers dc electrical characteristics the following table provides the ti mers dc electrical characteristics. table 69. timers dc electrical characteristics for recommended operating conditions, see ta bl e 3 parameter symbol min max unit notes input high voltage v ih 2?v 1 input low voltage v il ?0 . 8 v 1 input current (ovin = 0 v or ovin = ovdd) i in ? 4 0 a2 output high voltage (ov dd = min, i oh = ?2 ma) v oh 2.4 ? v ? output low voltage (ov dd = min, i ol = 2 ma) v ol ?0 . 4 v ? note: 1. the min v il and max v ih values are based on the respective min and max ov in values found in ta b l e 3 . 2. the symbol ov in represents the input voltage of the supply. it is referenced in ta bl e 3 . esdch t shsckr external clock vm vm vm t shsck t shsckf vm = midpoint voltage (ov dd /2) operational mode t shsckl t shsckh vm = midpoint voltage (ov dd /2) sd_ck external clock sd_dat/cmd vm vm vm vm inputs sd_dat/cmd outputs t shsivkh t shsixkh t shskhov
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 programmable interrupt controller (pic) freescale semiconductor 110 2.17.2 timers ac timing specifications the following table provides the timers input and output ac timing specifications. the following figure provides the ac test load for the timers. figure 63. timers ac test load 2.18 programmable interrupt controller (pic) this section describes the dc and ac electrical specifications for th e pic of the mpc8569e. 2.18.1 pic dc electrical characteristics the following table provides the dc electrical characteristics for the external interrupt pins irq [0:6], irq [8:11] and irq_out of the pic, as well as the port interrupts of the quicc engine block. table 70. timers input ac timing specifications for recommended operating conditions, see ta bl e 3 parameter symbol typ unit notes timers inputs?minimum pulse width t tiwid 20 ns 1, 2 notes: 1. input specifications are measured from th e 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2. timers inputs and outputs are asynchronous to any visible cl ock. timers outputs must be synchronized before use by any external synchronous logic. timers inputs are required to be valid for at least t tiwid ns to ensure proper operation. table 71. pic dc electrical characteristics for recommended operating conditions, see ta bl e 3 parameter symbol min max unit notes input high voltage v ih 2?v 1 input low voltage v il ?0 . 8 v 1 input current (ov in = 0 v or ov in = ov dd )i in ? 4 0 a2 output high voltage (ov dd = min, i oh = ?2 ma) v oh 2.4 ? v ? output low voltage (ov dd = min, i ol = 2 ma) v ol ?0 . 4 v ? note: 1. the min v il and max v ih values are based on the respective min and max ov in values found in ta b l e 3 . 2. the symbol ov in represents the input voltage of the supply. it is referenced in ta bl e 3 . output z 0 = 50 ov dd /2 r l = 50
spi interface mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 111 2.18.2 pic ac timing specifications the following table provides the pic input and output ac timing specifications. 2.19 spi interface this section describes the spi dc and ac electrical specifications of the mpc8569e. 2.19.1 spi dc electrical characteristics the following table provides the spi dc electrical characteristics. 2.19.2 spi ac timing specifications the following table and provide the spi in put and output ac timing specifications. table 72. pic input ac timing specifications for recommended operating conditions, see ta bl e 3 parameter symbol min max unit notes pic inputs?minimum pulse width t piwid 3 ? sysclk 1 note: 1. pic inputs and outputs are asynchronous to any visible clock. pic outputs must be synchronized before use by any external synchronous logic. pic inputs are required to be valid for at least t piwid ns to ensure proper operation when working in edge-triggered mode. table 73. spi dc electrical characteristics for recommended operating conditions, see ta bl e 3 parameter symbol min max unit notes input high voltage v ih 2.0 ? v 1 input low voltage v il ?0.8 v 1 input current (ov in = 0 v or ov in = ov dd )i in ? 40 a2 output high voltage (ov dd = min, i oh = ?2 ma) v oh 2.4 ? v ? output low voltage (ov dd = min, i oh = 2 ma) v ol ?0.4 v ? note: 1. the min v il and max v ih values are based on the respective min and max ov in values found in ta b l e 3 . 2. the symbol ov in represents the input voltage of the supply. it is referenced in ta bl e 3 . table 74. spi ac timing specifications for recommended operating conditions, see ta bl e 3 parameter symbol 1 min max unit note spi outputs valid?master mode (internal clock) delay t nikhov ?6ns2 spi outputs hold?master mode (internal clock) delay t nikhox 0.5 ? ns 2 spi outputs valid?slave mode (external clock) delay t nekhov ?9ns2 spi outputs hold?slave mode (external clock) delay t nekhox 2?ns2
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 spi interface freescale semiconductor 112 the following figure provides the ac test load for the spi. figure 64. spi ac test load figure 65 and figure 66 represent the ac timing from table 74 . note that although the specifi cations generally reference the rising edge of the clock, these ac timing diagrams al so apply when the falling edge is the active edge. the following figure shows the spi timing in slave mode (external clock). figure 65. spi ac timing in slave mode (external clock) diagram spi inputs?master mode (internal clock) input setup time t niivkh 4?ns? spi inputs?master mode (internal clock) input hold time t niixkh 0?ns? spi inputs?slave mode (external clock) input setup time t neivkh 4?ns? spi inputs?slave mode (external clock) input hold time t neixkh 2?ns? note: 1 the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t nikhox symbolizes the internal timing (ni) for the time spiclk clock reference (k) goes to the high state (h ) until outputs (o) are invalid (x). 2. output specifications are me asured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings ar e measured at the pin. table 74. spi ac timing specifications (continued) for recommended operating conditions, see ta bl e 3 parameter symbol 1 min max unit note output z 0 = 50 ov dd /2 r l = 50 spiclk (output) t neixkh t nekhov input signals: spimiso (see note) output signals: spimosi (see note) t neivkh t nekhox note: the clock edge is selectable on spi.
tdm/si mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 113 the following figure shows the spi timing in master mode (internal clock). figure 66. spi ac timing in master mode (internal clock) diagram 2.20 tdm/si this section describes the dc and ac electrical specifications for the time-division-multiplexed and serial interface of the mpc8569e. 2.20.1 tdm/si dc electrical characteristics the following table provides the dc electrical characteristi cs for the mpc8569e tdm/si. 2.20.2 tdm/si ac timing specifications the following table provides the tdm/si input and output ac timing specifications. note: rise/fall time on qe input pins the rise / fall time on qe i nput pins should not exceed 5n s. this must be enforced especially on clock signals. rise time refers to signal transitions from 10% to 90% of vcc; fall time refers to transitions from 90% to 10% of vcc. table 75. tdm/si dc electrical characteristics characteristic symbol min max unit notes output high voltage (ov dd = min, i oh = ?2 ma) v oh 2.4 ? v ? output low voltage (ov dd = min, i oh = 2 ma) v ol ?0 . 4v? input high voltage v ih 2.0 ov dd +0.3 v ? input low voltage v il ?0.3 0.8 v ? input current (0 v v in ov dd )i in ? 4 0 a1 note: 1. the symbol v in , in this case, represents the ov in referenced in ta b l e 2 and ta bl e 3 . spiclk (output) t niixkh t nikhov input signals: spimiso (see note) output signals: spimosi (see note) t niivkh t nikhox note: the clock edge is selectable on spi.
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 tdm/si freescale semiconductor 114 the following figure provides the ac test load for the tdm/si. figure 67. tdm/si ac test load the below figure represents the ac timing from table 76 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagra ms also apply when the falling edge is the active edge. the following figure shows the tdm/si timing with external clock. figure 68. tdm/si ac timing (external clock) diagram table 76. tdm/si ac timing specifications 1 characteristic symbol 2 min max unit tdm/si outputs?external clock delay t sekhov 21 1n s tdm/si outputs?external clock high impedance t sekhox 21 0n s tdm/si inputs?external clock input setup time t seivkh 5?n s tdm/si inputs?external clock input hold time t seixkh 2?n s notes: 1. output specifications are meas ured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing spec ifications follow the pattern t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t sekhox symbolizes the tdm/si outputs external timing (se) for the time t tdm/si memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). output z 0 = 50 ov dd /2 r l = 50 tdm/siclk (input) t seixkh t seivkh t sekhov input signals: tdm/si (see note) output signals: tdm/si (see note) t sekhox note: the clock edge is selectable on tdm/si.
usb interface mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 115 2.21 usb interface this section provides the ac and dc electrical sp ecifications for the usb in terface of the mpc8569e. 2.21.1 usb dc electrical characteristics the following table provides the usb dc electrical characteristics. 2.21.2 usb ac electrical specifications the following table describes the general usb timing specifications. table 77. usb dc electrical characteristics for recommended operating conditions, see ta bl e 3 parameter symbol min max unit notes input high voltage v ih 2?v1 input low voltage v il ?0 . 8v1 input current (ov in = 0 v or ov in = ov dd )i in ? 4 0 a2 output high voltage (ov dd = min, i oh = ?2 ma) v oh 2.8 ? v ? output low voltage (ov dd = min, i ol = 2 ma) v ol ?0 . 3v? differential input sensitivity v di 0.2 ? v 3 differential common mode range v cm 0.8 2.5 v 3 note: 1. the min v il and max v ih values are based on the respective min and max ov in values found in ta b l e 3 . 2. the symbol ov in represents the input voltage of the supply. it is referenced in ta bl e 3 . 3. applies to low/full speed table 78. usb general timing parameters for recommended operating conditions, see ta bl e 3 parameter symbol 1 min max unit notes usb clock cycle time t usck 20.83 ? ns full speed 48 mhz usb clock cycle time t usck 166.67 ? ns low speed 6 mhz skew between txp and txn t ustspn ?5n s2 skew among rxp, rxn, and rxd t usrspnd ? 10 ns full-speed transitions, 2 skew among rxp, rxn, and rxd t usrpnd ? 100 ns low-speed transitions, 2 notes: 1. the symbols used for timing specifications follow the pattern t (first two letters of functional block)(state)(signal) for receive signals and t (first two letters of functional block)(state)(signal) for transmit signals. for example, t usrspnd symbolizes usb timing (us) for the usb receive signals skew (rs) among rxp, rxn, and rxd (pnd). also, t ustspn symbolizes usb timing (us) for the usb transmit signals skew (ts) between txp and txn (pn). 2. skew measurements are done at ov dd /2 of the rising or falling edge of the signals.
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 utopia/pos interface freescale semiconductor 116 the following figure provide the ac test load for the usb. figure 69. usb ac test load 2.22 utopia/pos interface this section describes the dc and ac electrical specifications for the utopia interface. 2.22.1 utopia/pos dc electrical characteristics the following table provides th e dc electrical characteristics. 2.22.2 utopia/pos ac timing specifications the following table provides the utopia/pos input and output ac timing specifications. table 79. utopia/pos dc electrical characteristics for recommended operating conditions, see ta bl e 3 parameter symbol min max unit notes input high voltage v ih 2?v 1 input low voltage v il ?0 . 8 v 1 input current (ov in = 0 v or ov in = ov dd )i in ? 4 0 a2 output high voltage (ov dd = min, i oh = ?2 ma) v oh 2.4 ? v ? output low voltage (ov dd = min, i ol = 2 ma) v ol ?0 . 4 v ? note: 1. the min v il and max v ih values are based on the respective min and max ov in values found in ta b l e 3 . 2. the symbol ov in represents the input voltage of th e supply. it is referenced in ta b l e 3 . table 80. utopia/pos ac timing specifications 1 characteristic symbol 2 min max unit utopia/pos outputs?internal clock delay t uikhov 08 . 0n s utopia/pos outputs?external clock delay t uekhov 1.0 10.0 ns utopia/pos outputs?internal clock high impedance t uikhox 08 . 0n s utopia/pos outputs?exter nal clock high impedance t uekhox 1.0 10.0 ns utopia/pos inputs?internal clock input setup time t uiivkh 6.4 ? ns output z 0 = 50 ov dd /2 r l = 50
utopia/pos interface mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 117 the following figure provides the ac test load for the utopia/pos. figure 70. utopia/pos ac test load figure 71 and figure 72 represent the ac timing from table 80 . note that although the specifi cations generally reference the rising edge of the clock, these ac timing diagrams al so apply when the falling edge is the active edge. the following figure shows the utopia/pos timing with external clock. figure 71. utopia/pos ac timing (external clock) diagram utopia/pos inputs?externa l clock input setup time t ueivkh 4.0 ? ns utopia/pos inputs?internal clock input hold time t uiixkh 0?n s utopia/pos inputs?external clock input hold time t ueixkh 1.2 ? ns notes: 1. output specifications are meas ured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing spec ifications follow the pattern t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t uikhox symbolizes the utopia/pos outputs internal timing (ui) for the time t utopia memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). table 80. utopia/pos ac timing specifications 1 (continued) characteristic symbol 2 min max unit output z 0 = 50 ov dd /2 r l = 50 utopiaclk (input) t ueixkh t ueivkh t uekhov input signals: utopia output signals: utopia t uekhox
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 thermal characteristics freescale semiconductor 118 the following figure shows the utopia/pos timing with internal clock. figure 72. utopia/pos ac timi ng (internal clock) diagram 3 thermal this section describes the thermal specifications of the mpc8569e. 3.1 thermal characteristics the following table provides the package thermal characteristics of the mpc8569e. 3.2 recommended thermal model information about flotherm models of the package or thermal data not available in this document can be obtained from your local freescale sales office. table 81. package thermal characteristics characteristic jedec board symbol value unit notes junction-to-ambient natural convection single layer board (1s) r ja 16 c/w 1, 2 junction-to-ambient natural convection four layer board (2s2p) r ja 12 c/w 1, 2 junction-to-ambient (at 200 ft/min) single layer board (1s) r ja 12 c/w 1, 2 junction-to-ambient (at 200 ft/min) four layer board (2s2p) r ja 9 c/w 1, 2 junction-to-board thermal ? r jb 5 c/w 3 junction-to-case thermal ? r jc 1.0 c/w 4 notes: 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissi pation of other components on the board, and board thermal resistance. 2. per jedec jesd51-2 and jesd51-6 with the board (jesd51-9) horizontal. 3. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 4. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plat e temperature is used for the case temperature. reported value includes the thermal resistance of the interface layer. utopiaclk (output) t uiixkh t uikhov input signals: utopia output signals: utopia t uiivkh t uikhox
thermal management information mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 119 3.3 thermal management information this section provides thermal management information for the flip chip plastic ball grid array (fc-pbga) package for air-cooled applications. pr oper thermal control design is primarily dependent on the system-level design?the heat sink, airflow , and thermal interface material. the recommended attachment method to the heat sink is illustrated in the following figure. the heat sink must be attached to the printed-circuit board with the spring force centered over the package. this spring for ce should not exceed 10 pounds force (45 newtons). figure 73. package exploded cross-sectional view the system board designer can choose among several types of co mmercially-available heat sinks to determine the appropriate one to place on the device. ultimately, the final selection of an appropriate heat si nk depends on factors such as thermal performance at a given air velocity, spatial volu me, mass, attachment method, assembly, and cost. 3.3.1 internal package conduction resistance for the package, the intrinsic internal conduction thermal resistance paths are as follows: ? the die junction-to-case thermal resistance ? the die junction-to-board thermal resistance adhesive or heat sink fc-pbga package heat sink clip printed-circuit board thermal interface material die die lid
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 package parameters for the mpc8569e freescale semiconductor 120 the following figure depicts the primary heat transfer path for a package with an att ached heat sink mounted to a printed-circu it board. figure 74. package with heat sink mounted to a printed-circuit board the heat sink removes most of the heat from the device. heat generated on the active side of the chip is conducted through the silicon and the heat sink attach material (or thermal interface material ), and to the heat sink. the junction-to-case thermal resistance is low enough that the heat sink attach material and heat si nk thermal resistance are the dominant terms. 3.3.2 thermal interface materials a thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. the performance of thermal in terface materials improves with in creased contact pressure; this pe rformance characteristic chart is generally provided by the thermal interface vendor. the recomme nded method of mounting heat sinks on the package is by means of a spring clip attachment to the printed-circuit board (see figure 73 ). the system board designer can choose among several type s of commercially-available thermal interface materials. 4 package description the following section describes the detailed cont ent and mechanical desc ription of the package. 4.1 package parameters for the mpc8569e the following table provides the package parameters for the fc-pbga. the package type is 29 mm 29 mm, 783 plastic ball grid array (fc-pbga). table 82. package parameters parameter pbga package outline 29 mm 29 mm external resistance external resistance internal resistance radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package (note the internal versus external package resistance.)
package parameters for the mpc8569e mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 121 interconnects 783 ball pitch 1 mm ball diameter (typical) 0.6 mm solder ball (lead-free) 96.5% sn 3% ag 0.5% cu table 82. package parameters (continued) parameter pbga
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 mechanical dimensions of the fc-pbga with full lid freescale semiconductor 122 4.2 mechanical dimensions of the fc-pbga wi th full lid the following figure shows the mechan ical dimensions and bottom surface nom enclature for the mpc8569e fc-pbga package with full lid. notes: 1 all dimensions are in millimeters. 2 dimensions and tolerances per asme y14.5m-1994. 3 maximum solder ball diameter measured parallel to datum a. 4 datum a, the seating plane, is determined by the spherical crowns of the solder balls. 5 parallelism measurement shall exclude any effect of mark on top surface of package. 6 all dimensions are symmetric across the packa ge center lines unless dimensioned otherwise. 7 29.2 mm maximum package assembly (lid and laminate) x and y. figure 75. mpc8569e fc-pbga package with full lid
part numbers fully addressed by this document mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 123 5 ordering information contact your local freescale sales office or regi onal marketing team for ordering information. ordering information for the parts fully covered by this specification document is provided in section 5.1, ?part numbers fully addressed by this document .? 5.1 part numbers fully ad dressed by this document the following table show s the device nomenclature. table 83. device nomenclature mpc nnnn e c vt aa x g r prod- uct code 1 part identifier security engine temperature range package 2 processor frequency 3 ddr frequency 4 qe frequency revision level mpc ppc 8569 e = included blank = 0 to 105 c c = ?40 to 105 c vt = pb free, fc-pbga an = 800 mhz aq = 1067 mhz au = 1333 mhz k = 600 mhz l = 667 mhz n = 800 mhz g = 400 mhz j = 533 mhz l = 667 mhz blank = rev. 1.0 (svr = 0x8088_0010 a = rev. 2.0 (svr = 0x8088_0020 b = rev. 2.1 (svr = 0x8088_0021 blank = not included a = rev. 2.0 (svr = 0x8080_0020 b = rev. 2.1 (svr = 0x8080_0021 notes: 1. mpc stands for ?qualified.? ppc st ands for pre-production samples. 2. see section 4, ?package description,? for more information on available package types. 3. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specifica tion support all core frequencies. additionally, parts addressed by part number specifications may support other maximum core frequencies. 4. see ta b l e 8 4 for the corresponding maximum platform frequency.
mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 part marking freescale semiconductor 124 5.2 part marking parts are marked as the example shown in the following figure. figure 76. part marking for fc-pbga device 5.3 part numbering the following table list all part numbers that are offered for mpc8569e. 6 product documentation the following documents are required for a complete description of the device and are needed to design properly with the part. ? mpc8569e powerquicc iii integrated processor reference manual (document number: mpc8569erm) ? e500 powerpc core reference manual (document number: e500corerm) ? quicc engine block reference manual with protocol interworking (document number: qeiwrm) table 84. mpc8569 part numbers core / ddr / qe / platform (mhz) standard temp without security standard temp with security extended temp without security extended temp with security note 800 / 600 / 400 / 400 mpc8569vtankg mpc8569evtankg mpc8569cvtankg mpc8569ecvtankg 1, 2 1067 / 667/ 533 / 533 mpc8569vtaqlj mpc8569evtaqlj mpc8569cvtaqlj mpc8569ecvtaqlj 1, 2 1333 / 800 / 667 / 533 mpc8569vtaunl mpc8569evtaunl ? ? 1, 2 notes: 1. standard temperature and extended temperature with security parts are available for pre-prod uction samples. the prefix is ppc instead of mpc. 2. part numbers that end with a ?blank? indicate rev 1.0 silicon ; part numbers that end with an ?a? are rev 2.0 silicon; part n umbers that end with a ?b? are rev 2.1 silicon. mmmmm ccccc atwlyyww notes : mmmmm is the mask number. fc-pbga mpc8569xxxxxx mpc8569xxxxxx is the orderable part number. ccccc is the country of assembly. this space is left blank if atwlyyww is the traceability code. parts are assembled in the united states.
part numbering mpc8569e powerquicc iii integrated pro cessor hardware specifications, rev. 0 freescale semiconductor 125 7 document revision history the following table provides a revision history for this document. table 85. document revision history revision date substantive change(s) 0 06/2011 initial public release
document number: mpc8569eec rev. 0 06/2011 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800-441-2447 or +303-675-2140 fax: +303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale, the freescale logo, and powerquicc are trademarks of freescale semiconductor, inc. reg. u. s. pat. & tm. off. quicc engine is a trademark of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? 2008?2011 freescale semiconductor, inc.

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